中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

55 records (took 0.021 seconds)

    Core prioritization for heterogeneous on-chip networks
    41.
    发明授权
    Core prioritization for heterogeneous on-chip networks 有权

    公开(公告)号：US10445131B2

    公开(公告)日：2019-10-15

    申请号：US15306004

    申请日：2014-04-24

    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

    Inventor： Yan Solihin

    IPC: G06F9/46 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/3296 ,  G06F9/50 ,  G06F9/455

    Abstract: A processor may comprise a plurality of cores operating at heterogeneous frequencies communicatively coupled by a network of routers also operating at heterogeneous frequencies. A core may be prioritized for thread execution based on operating frequencies of routers on a path from the core to a memory controller. Relatively higher priority may be assigned to cores having a path comprising only routers operating at a relatively higher frequency. A combined priority for thread execution may be based on core frequency, router frequency, and the frequency of routers on a path from the core to a memory controller. A core may be selected based primarily on core operating frequency when cache misses fall below a threshold value.

    DIRECTORY COHERENCE FOR MULTICORE PROCESSORS
    47.
    发明申请
    DIRECTORY COHERENCE FOR MULTICORE PROCESSORS 审中-公开
    多媒体处理器的目录一致

    公开(公告)号：US20170046263A1

    公开(公告)日：2017-02-16

    申请号：US15306021

    申请日：2014-04-24

    Applicant: Empire Technology Development LLC

    Inventor： Yan Solihin

    IPC: G06F12/0811 ,  G06F12/0817

    CPC classification number: G06F12/0811 ,  G06F12/0817 ,  G06F12/0826 ,  G06F2212/1028 ,  G06F2212/621 ,  G06F2212/622 ,  Y02D10/13

    Abstract: A cache coherence mechanism may comprise a bit-to-cache map for processor cores operable up to a maximum frequency for cores of a multicore processor. Entries in a cache coherence directory may include a bit field identifying cores operable at or near the maximum frequency that share a memory block corresponding to the entry. An additional field may indicate sharing by cores operating at lower frequencies. The additional field may be indicative of the bit-field corresponding to a bit-to-cache map representative of cores other than those operating at or near the maximum frequency.

    Abstract translation: 高速缓存一致性机制可以包括针对多核处理器的核的最高频率可操作的处理器核的位到高速缓存映射。 高速缓存一致性目录中的条目可以包括标识可在共享对应于条目的存储器块的最大频率处或附近操作的核的位字段。 附加字段可以指示以更低频率操作的核的共享。 附加字段可以指示对应于表示除了在最大频率处或接近最大频率处操作的核心的核的位到高速缓存映射的位域。

    Resource allocation in multi-core architectures
    48.
    发明授权
    Resource allocation in multi-core architectures 有权
    多核架构中的资源分配

    公开(公告)号：US09471381B2

    公开(公告)日：2016-10-18

    申请号：US14657716

    申请日：2015-03-13

    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

    Inventor： Yan Solihin

    IPC: G06F9/46 ,  G06F9/50

    CPC classification number: G06F9/5016 ,  G06F9/50 ,  G06F9/5005 ,  G06F2209/5018 ,  G06F2209/503

    Abstract: Technologies are generally described for a method, device and architecture effective to allocate resources. In an example, the method may include associating first and second resources with first and second resource identifiers and mapping the first and second resource identifiers to first and second sets of addresses in a memory, respectively. The method may include identifying that the first resource is at least partially unavailable. The method may include mapping the second resource identifier to at least one address of the first set of addresses in the memory when the first resource is identified as at least partially unavailable. The method may include receiving a request for the first resource, wherein the request identifies a particular address of the addresses in the first set of addresses. The method may include analyzing the particular address to identify a particular resource and allocating the request to the particular resource.

    Abstract translation: 技术通常描述为有效分配资源的方法，设备和架构。 在一个示例中，该方法可以包括将第一和第二资源与第一和第二资源标识符相关联，并且将第一和第二资源标识符分别映射到存储器中的第一和第二组地址。 该方法可以包括识别第一资源至少部分不可用。 该方法可以包括当第一资源被识别为至少部分不可用时，将第二资源标识符映射到存储器中的第一组地址的至少一个地址。 该方法可以包括接收对第一资源的请求，其中该请求标识第一组地址中的地址的特定地址。 该方法可以包括分析特定地址以识别特定资源并将该请求分配给特定资源。

    Memory allocation accelerator
    49.
    发明授权
    Memory allocation accelerator 有权
    内存分配加速器

    公开(公告)号：US09465729B2

    公开(公告)日：2016-10-11

    申请号：US13982807

    申请日：2013-03-13

    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

    Inventor： Yan Solihin

    IPC: G06F3/00 ,  G06F12/00 ,  G06F12/02

    CPC classification number: G06F12/0292 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0673 ,  G06F12/0223 ,  G06F12/023

    Abstract: Technologies are generally described for methods and systems effective to implement a memory allocation accelerator. A processor may generate a request for allocation of a requested chunk of memory. The request may be received by a memory allocation accelerator configured to be in communication with the processor. The memory allocation accelerator may process the request to identify an address for a particular chunk of memory corresponding to the request and may return the address to the processor.

    Abstract translation: 通常描述有效实现内存分配加速器的方法和系统的技术。 处理器可以产生对所请求的存储器块的分配的请求。 该请求可以被配置为与处理器通信的存储器分配加速器来接收。 存储器分配加速器可以处理该请求以识别与该请求对应的特定存储块的地址，并且可以将该地址返回给处理器。

    DATA STORAGE BASED ON MEMORY PERSISTENCY
    50.
    发明申请
    DATA STORAGE BASED ON MEMORY PERSISTENCY 有权
    基于存储器持续存储的数据存储

    公开(公告)号：US20160170897A1

    公开(公告)日：2016-06-16

    申请号：US14567278

    申请日：2014-12-11

    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

    Inventor： Yan Solihin

    IPC: G06F12/10

    CPC classification number: G06F12/1009 ,  G06F11/1446 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0897 ,  G06F2212/1032 ,  G06F2212/205 ,  G06F2212/311 ,  G06F2212/502 ,  G06F2212/657

    Abstract: Technologies are generally described for methods and systems effective to store data in a memory module. The memory module may include a volatile portion and a non-volatile portion. The methods may comprise receiving, by a processor, a request to store the data. The request may include an indication of a virtual address. The methods may further include determining, by the processor, a persistency of the data based on the virtual address. The methods may further include performing a first operation of identifying a particular portion of the memory module based on the virtual address. The methods may further include generating a command to store the data in the particular portion of the memory module. The methods may further include controlling the operating system to perform a second operation of updating a translation lookaside buffer to indicate the persistency of the data.

    Abstract translation: 一般来讲，有效地将数据存储在存储器模块中的方法和系统的技术。 存储器模块可以包括易失性部分和非易失性部分。 该方法可以包括由处理器接收存储数据的请求。 该请求可以包括虚拟地址的指示。 所述方法还可以包括由处理器基于虚拟地址确定数据的持久性。 所述方法还可以包括基于所述虚拟地址执行识别所述存储器模块的特定部分的第一操作。 所述方法还可以包括生成用于将数据存储在存储器模块的特定部分中的命令。 所述方法还可以包括控制操作系统以执行更新翻译后备缓冲器以指示数据的持续性的第二操作。

Patent Agency Ranking