公开(公告)号：US09601513B1

公开(公告)日：2017-03-21

申请号：US14977899

申请日：2015-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Terence B. Hook ,  Andreas Scholze ,  Lars W. Liebmann ,  Roger A. Quon ,  Andrew H. Simon

IPC: H01L27/12 ,  H01L23/528 ,  H01L21/84 ,  H01L29/06 ,  H01L21/266 ,  H01L21/3115 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L27/1211 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/743 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/84 ,  H01L21/845 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/535 ,  H01L29/0649

Abstract: Various embodiments include methods and integrated circuit structures. One method includes masking a structure with a mask to cover at least a portion of the structure under the mask, selectively implanting a material through a semiconductor layer and into a buried insulator layer forming an implant region. The implant region is substantially parallel to and below an upper surface of the structure. The method may also include masking an additional portion of the structure; etching a set of access ports though the semiconductor layer and partially through the insulator layer into the implant region; etching at least one tunnel below the upper surface of the structure in the implant region using the set of access; and depositing a conductor into the at least one tunnel and the set of access ports.

公开(公告)号：US09570573B1

公开(公告)日：2017-02-14

申请号：US14822490

申请日：2015-08-10

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Su Chen Fan ,  Lars W. Liebmann ,  Ruilong Xie

IPC: H01L29/45 ,  H01L21/768 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L23/535 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/7827 ,  H01L2221/1063

Abstract: A method for forming a gate tie-down includes exposing an active area to form trench contact openings and forming trench contacts therein. An etch stop layer is formed on the trench contacts and on spacers of adjacent gate structures. An interlevel dielectric (ILD) is deposited to fill over the etch stop layer. The ILD and the etch stop layer on one side of the gate structure are opened up to provide an exposed etch stop layer portion. The gate structure is recessed to expose a gate conductor. The exposed etch stop layer portion is removed. A conductive material is deposited to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact.

Abstract translation: 形成栅极结合的方法包括暴露有源区以形成沟槽接触开口并在其中形成沟槽接触。 在沟槽触点和相邻栅极结构的间隔物上形成蚀刻停止层。 沉积层间电介质（ILD）以填满蚀刻停止层。 栅极结构的一侧上的ILD和蚀刻停止层被打开以提供暴露的蚀刻停止层部分。 栅极结构凹陷以露出栅极导体。 去除暴露的蚀刻停止层部分。 沉积导电材料以提供与栅极结构一侧上的沟槽接触的自对准接触，以形成到栅极导体下方的栅极接触，并且在ILD之间的有效区域之间形成水平连接 栅极导体和自对准触点。

公开(公告)号：US10522654B2

公开(公告)日：2019-12-31

申请号：US16120870

申请日：2018-09-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/027 ,  H01L23/535 ,  H01L27/11 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.

公开(公告)号：US10522403B2

公开(公告)日：2019-12-31

申请号：US15868479

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jason E. Stephens ,  Daniel Chanemougame ,  Ruilong Xie ,  Lars W. Liebmann ,  Gregory A. Northrop

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

公开(公告)号：US10332803B1

公开(公告)日：2019-06-25

申请号：US15973817

申请日：2018-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Edward J. Nowak ,  Bipul C. Paul ,  Steven R. Soss ,  Julien Frougier ,  Daniel Chanemougame ,  Lars W. Liebmann

IPC: H01L21/8238 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092

Abstract: Various embodiments relate to gate-all-around (GAA) transistors and methods of forming such transistors. In some embodiments, a method performed on a precursor structure includes selectively removing a sacrificial nanosheet to open a vertical gap between a pair of semiconductor nanosheets; forming a first work function metal to surround the precursor nanosheet stack and fin, the first work function metal filling the vertical gap between the pair of semiconductor nano sheets; selectively removing first work function metal surrounding the fin while preserving an entirety of first work function metal surrounding the nanosheet stack; and forming a second work function metal: over a remaining portion of the first work function metal on nanosheet stack, and surrounding the fin, where first work function metal includes a different material than second work function metal.

公开(公告)号：US20190181042A1

公开(公告)日：2019-06-13

申请号：US15837671

申请日：2017-12-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars W. Liebmann ,  Balasubramanian Pranatharthi Haran ,  Veeraraghavan Basker

IPC: H01L21/768 ,  H01L21/321

Abstract: One illustrative method disclosed includes, among other things, forming at least one layer of sacrificial material above an underlying conductive structure, forming a sacrificial contact structure in the at least one layer of sacrificial material and forming at least one layer of insulating material around the sacrificial contact structure. In this example, the method also includes performing at least one process operation to expose an upper surface of the sacrificial contact structure, removing the sacrificial contact structure so as to form a contact opening that exposes the upper surface of the underlying conductive structure and forming a final contact structure in the contact opening, the final contact structure conductively contacting the underlying conductive structure.

公开(公告)号：US10290544B2

公开(公告)日：2019-05-14

申请号：US15728632

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars W. Liebmann ,  Daniel Chanemougame ,  Chanro Park

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  H01L23/528

Abstract: One illustrative method disclosed herein may include forming a contact etching structure in a layer of insulating material positioned above first and second lower conductive structures, wherein at least a portion of the contact etching structure is positioned laterally between the first and second lower conductive structures, forming a first conductive line and a first conductive contact adjacent a first side of the contact etching structure and forming a second conductive line and a second conductive contact adjacent a second side of the contact etching structure, wherein a spacing between the first and second conductive lines is approximately equal to a dimension of the contact etching structure.

公开(公告)号：US20180315821A1

公开(公告)日：2018-11-01

申请号：US15581053

申请日：2017-04-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hao Tang ,  Cheng Chi ,  Daniel Chanemougame ,  Lars W. Liebmann ,  Mark V. Raymond

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535 ,  H01L29/78 ,  H01L29/45

Abstract: One illustrative method disclosed includes, among other things, forming a conductive source/drain metallization structure adjacent a gate, forming a gate contact opening that exposes at least a portion of a front face of the conductive source/drain metallization structure and a portion of an upper surface of a gate structure of the gate. In this example, the method further includes forming an internal insulating spacer within the gate contact opening that is positioned on and in contact with the exposed portion of the front face, wherein the spacer leaves at least a portion of the upper surface of the gate structure exposed, and forming a conductive gate contact structure (CB) in the conductive gate contact opening.

公开(公告)号：US20180151433A1

公开(公告)日：2018-05-31

申请号：US15880059

申请日：2018-01-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/027 ,  H01L27/11 ,  H01L23/535 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US09929049B2

公开(公告)日：2018-03-27

申请号：US15699322

申请日：2017-09-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528 ,  H01L21/311 ,  H01L27/11 ,  H01L23/535 ,  H01L21/027

CPC classification number: H01L29/66553 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.