公开(公告)号：US20170330878A1

公开(公告)日：2017-11-16

申请号：US15154087

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shesh Mani Pandey

IPC: H01L27/088 ,  H01L29/51 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823487 ,  H01L29/0847 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7834

Abstract: A FinFET-type device is formed having a fin structure with vertically-oriented source/drain regions (with lightly doped extensions) and a channel region extending substantially perpendicular to the surface of the semiconductor substrate. A semiconductor stack is provided (or formed) having a first heavily doped layer and two lightly doped layer, with a channel region formed between the two lightly doped layers. The stack is etched to form fin structures (for the devices) and a gate stack is formed along the sidewalls of the channel region. A second heavily doped layer is selectively formed on the upper lightly doped layer. A portion of the first heavily doped layer and a portion of the lower lightly doped layer form a lower S/D region with a lightly doped extension region. Similarly, a portion of the second heavily doped layer and a portion of the upper lightly doped layer form an upper S/D region with a lightly doped extension region.

公开(公告)号：US20170309623A1

公开(公告)日：2017-10-26

申请号：US15135358

申请日：2016-04-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shesh Mani Pandey ,  Baofu Zhu

IPC: H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/67

CPC classification number: H01L27/0886 ,  H01L21/67155 ,  H01L21/823431 ,  H01L29/1037 ,  H01L29/66818 ,  H01L29/7853

Abstract: We disclose semiconductor devices, comprising a semiconductor substrate comprising bulk silicon; and a plurality of fins formed on the semiconductor substrate; wherein each of the plurality of fins comprises a lower portion disposed on the semiconductor substrate and having a first width, and an upper portion disposed on the lower portion and having a second width, wherein the second width is greater than the first width, as well as methods, apparatus, and systems for fabricating such semiconductor devices.

公开(公告)号：US20170294522A1

公开(公告)日：2017-10-12

申请号：US15092168

申请日：2016-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani Pandey ,  Muhammad Rahman ,  Srikanth Balaji Samavedam

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L21/306

CPC classification number: H01L29/66795 ,  H01L21/265 ,  H01L21/306 ,  H01L29/0847 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, forming a gate structure around the fin and, after forming the gate structure, forming a final source/drain cavity in the fin, wherein the source/drain cavity comprises an upper innermost edge and a lower innermost edge, both of which extend laterally under at least a portion of the gate structure, and wherein the lower innermost edge extends laterally further under the gate structure than does the upper innermost edge. The method also includes performing an epitaxial growth process to form an epi semiconductor material in the final source/drain cavity

公开(公告)号：US09559176B2

公开(公告)日：2017-01-31

申请号：US15180312

申请日：2016-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie Feng ,  Yanxiang Liu ,  Shesh Mani Pandey ,  Jianwei Peng ,  Francis Benistant

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/45 ,  H01L27/092 ,  H01L21/285 ,  H01L21/324 ,  H01L21/8234

CPC classification number: H01L29/41791 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28512 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/785

Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.

Abstract translation: 公开了一种形成具有突然垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第一掩模; 在栅电极的每一侧上在第二极性FET的鳍的相对侧上形成间隔物，第二极性与第一极性相反; 将第一掺杂剂注入到第二极性FET的鳍中; 在栅电极的每一侧蚀刻第二极性FET的鳍的空腔; 去除第一个面罩; 进行快速热退火（RTA）; 在每个空腔中外延生长第二极性FET的源极/漏极区域; 在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第二掩模; 以及在所述第二极性FET的源极/漏极区域中注入第二掺杂剂。

公开(公告)号：US09397162B1

公开(公告)日：2016-07-19

申请号：US14679074

申请日：2015-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie Feng ,  Yanxiang Liu ,  Shesh Mani Pandey ,  Jianwei Peng ,  Francis Benistant

IPC: H01L21/82 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/324 ,  H01L21/3065 ,  H01L21/02 ,  H01L27/092 ,  H01L29/24

CPC classification number: H01L29/41791 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28512 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/785

Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.

Abstract translation: 公开了一种形成具有突然垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第一掩模; 在栅电极的每一侧上在第二极性FET的鳍的相对侧上形成间隔物，第二极性与第一极性相反; 将第一掺杂剂注入到第二极性FET的鳍中; 在栅电极的每一侧蚀刻第二极性FET的鳍的空腔; 去除第一个面罩; 进行快速热退火（RTA）; 在每个空腔中外延生长第二极性FET的源极/漏极区域; 在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第二掩模; 以及在所述第二极性FET的源极/漏极区域中注入第二掺杂剂。

公开(公告)号：US20200111713A1

公开(公告)日：2020-04-09

申请号：US16150651

申请日：2018-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Laertis Economikos ,  Shesh Mani Pandey ,  Chanro Park ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction. Parallel gate structures intersect the fins in a second direction perpendicular to the first direction, wherein the gate structures have a lower portion adjacent to the fins and an upper portion distal to the fins. Source/drain structures are positioned on the fins between the gate structures. Source/drain contacts are positioned on the source/drain structures and multiple insulator layers are positioned between the gate structures and the source/drain contacts. Additional upper sidewall spacers are positioned between the upper portion of the gate structures and the multiple insulator layers.

公开(公告)号：US20200091005A1

公开(公告)日：2020-03-19

申请号：US16134708

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qun Gao ,  Balaji Kannan ,  Shesh Mani Pandey ,  Haiting Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.

公开(公告)号：US20200075715A1

公开(公告)日：2020-03-05

申请号：US16121058

申请日：2018-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal Kamineni ,  Shesh Mani Pandey ,  Hui Zang

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/764 ,  H01L21/768

Abstract: One device disclosed herein includes, among other things, first and second active regions, a first source/drain contact positioned above the first active region, a second source/drain contact positioned above the second active region, and a dielectric material disposed between the first and second source/drain contacts, wherein the dielectric material defines an air gap cavity positioned between the first and second source/drain contacts.

公开(公告)号：US10475791B1

公开(公告)日：2019-11-12

申请号：US15994231

申请日：2018-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Garo Jacques Derderian ,  Laertis Economikos ,  Chun Yu Wong ,  Jiehui Shu ,  Shesh Mani Pandey

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234

Abstract: First and second fin-type field effect transistors (finFETs) are formed laterally adjacent one another extending from a top surface of an isolation layer. The first finFET has a first fin structure and the second finFET has a second fin structure. An insulator layer is on the first fin structure and the second fin structure. A gate conductor intersects the first fin structure and the second fin structure, and at least the insulator layer separates the gate conductor from the first fin structure and the second fin structure. Source and drain structures are on the first fin structure and the second fin structure laterally adjacent the gate conductor. The first fin structure has sidewalls that include a step and the second fin structure has sidewalls that do not include the step. The step is approximately parallel to the surface of the isolation layer.

公开(公告)号：US20190326165A1

公开(公告)日：2019-10-24

申请号：US15961337

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Daniel Chanemougame ,  Steven Soss ,  Lars Liebmann ,  Hui Zang ,  Shesh Mani Pandey

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528

Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.