公开(公告)号：US09129843B1

公开(公告)日：2015-09-08

申请号：US14302880

申请日：2014-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Richter ,  Peter Javorka ,  Jan Hoentschel

IPC: H01F17/00 ,  H01L49/02 ,  H01L21/263 ,  H01L21/762 ,  H01L27/06 ,  H01L29/06 ,  B23K26/00 ,  B23K26/38

CPC classification number: H01L28/10 ,  B23K26/38 ,  B23K26/53 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/32155 ,  H01L21/76224 ,  H01L27/0617 ,  H01L29/0653 ,  H01L29/66083 ,  H01L29/665 ,  H01L29/78 ,  H01L29/86

Abstract: A method of forming an inductor in a crystal semiconductor layer is provided, including generating an ion beam, directing the ion beam to a surface of the crystal semiconductor layer, applying a magnetic field to the ion beam to generate a helical motion of the ions and forming a three-dimensional helical structure in the crystal semiconductor layer by means of the ions of the ion beam.

Abstract translation: 提供一种在晶体半导体层中形成电感器的方法，包括产生离子束，将离子束引导到晶体半导体层的表面，向离子束施加磁场以产生离子的螺旋运动，以及 通过离子束的离子在晶体半导体层中形成三维螺旋结构。

公开(公告)号：US20130267044A1

公开(公告)日：2013-10-10

申请号：US13909221

申请日：2013-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

IPC: H01L21/66

CPC classification number: H01L22/10 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/7848 ,  Y02P80/30

Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.

Abstract translation: 在基于晶体管的基础上在半导体器件中形成高k金属栅极电极结构时，可以避免在N沟道晶体管的栅电极结构的端部处敏感材料的过度曝光，例如，在 在将应变诱导半导体材料并入P沟道晶体管的有源区域中，从而有助于提高预定晶体管特性和性能的产量。

公开(公告)号：US10049917B2

公开(公告)日：2018-08-14

申请号：US15269023

申请日：2016-09-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Philipp Steinmann ,  Peter Javorka

IPC: H01L21/762 ,  H01L27/12 ,  H01L21/3115 ,  H01L21/02 ,  H01L29/786

Abstract: Methods of locally changing the BOX layer of a MOSFET device to a high-k layer to provide different Vts with one backside voltage and the resulting device are provided. Embodiments include providing a Si substrate having a BOX layer formed over the substrate and a SOI layer formed over the BOX layer; implanting a high current of dopants into at least one portion of the BOX layer; performing a high-temperature anneal of the BOX layer; forming first and second fully depleted silicon-on-insulator (FDSOI) transistors on the SOI layer, the first FDSOI transistors formed above either the BOX layer or the at least one portion of the BOX layer and the second FDSOI transistors formed above the at least one portion of the BOX layer; and applying a single voltage across a backside of the Si substrate.

公开(公告)号：US09472642B2

公开(公告)日：2016-10-18

申请号：US14693978

申请日：2015-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Ralf Richter ,  Peter Javorka

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/283 ,  H01L29/78 ,  H01L29/06 ,  H01L29/45

CPC classification number: H01L29/665 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: The present disclosure provides in one aspect for a semiconductor device structure which may be formed by providing source/drain regions within a semiconductor substrate in alignment with a gate structure formed over the semiconductor substrate, wherein the gate structure has a gate electrode structure, a first sidewall spacer and a second sidewall spacer, the first sidewall spacer covering sidewall surfaces of the gate electrode structure and the sidewall spacer being formed on the first sidewall spacer. Furthermore, forming the semiconductor device structure may include removing the second sidewall spacer so as to expose the first sidewall spacer, forming a third sidewall spacer on a portion of the first sidewall spacer such that the first sidewall spacer is partially exposed, and forming silicide regions in alignment with the third sidewall spacer in the source/drain regions.

Abstract translation: 本公开在一个方面中提供了半导体器件结构，其可以通过在半导体衬底内提供与在半导体衬底上形成的栅极结构对准的源极/漏极区域形成，其中栅极结构具有栅电极结构，第一 侧壁间隔件和第二侧壁间隔件，所述第一侧壁间隔物覆盖所述栅极电极结构和所述侧壁间隔物的侧壁表面，所述侧壁间隔件形成在所述第一侧壁间隔物上。 此外，形成半导体器件结构可以包括去除第二侧壁间隔物以暴露第一侧壁间隔物，在第一侧壁间隔物的一部分上形成第三侧壁间隔物，使得第一侧壁间隔物部分地暴露，并且形成硅化物区域 与源极/漏极区域中的第三侧壁间隔物对准。

公开(公告)号：US20160276428A1

公开(公告)日：2016-09-22

申请号：US14658361

申请日：2015-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Juergen Faul ,  Peter Javorka

IPC: H01L29/06 ,  H01L29/66 ,  H03K17/687 ,  H01L21/762 ,  H01L21/28 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L21/76283 ,  H01L21/28035 ,  H01L21/28097 ,  H01L21/76254 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/4975 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/78624 ,  H01L29/78648 ,  H01L29/78654

Abstract: A semiconductor device is provided including a substrate, a buried oxide layer formed over the substrate, a semiconductor layer formed over the buried oxide layer, and a transistor device including a gate electrode, a gate insulation layer and a channel region, wherein the gate insulation layer comprises a part of the buried oxide layer.

Abstract translation: 提供了一种半导体器件，包括衬底，在衬底上形成的掩埋氧化物层，形成在掩埋氧化物层上的半导体层，以及包括栅电极，栅绝缘层和沟道区的晶体管器件，其中栅极绝缘 层包括一部分掩埋氧化物层。

公开(公告)号：US09343374B1

公开(公告)日：2016-05-17

申请号：US14527207

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Javorka ,  Stefan Flachowsky ,  Ralf Richter

IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L21/823864 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

Abstract: Forming a poly-Si device including pulling back spacers prior to silicidation and the resulting device are provided. Embodiments include forming two poly-Si gate stacks on an upper surface of a substrate; forming a hardmask over the second poly-Si gate stack; forming eSiGe with a silicon cap at opposite sides of the first poly-Si gate stack; removing the hardmask; forming nitride spacers at opposite sides of each of the poly-Si gate stacks; forming deep source/drain regions at opposite sides of the second poly-Si gate stack; forming a wet gap fill layer around each of the poly-Si gate stacks to a thickness less than the poly-Si gate stack height from the substrate's upper surface; removing an upper portion of the nitride spacers down to the height of the wet gap fill layer followed by removing the wet gap fill layer; and performing silicidation of the deep source/drain regions and the silicon cap.

Abstract translation: 形成包括在硅化之前拉回间隔物的多晶硅器件，并提供所得到的器件。 实施例包括在基板的上表面上形成两个多晶硅栅叠层; 在第二多晶硅栅叠层上形成硬掩模; 在所述第一多晶硅栅叠层的相对侧用硅帽形成eSiGe; 移除硬掩模; 在每个多晶硅栅极堆叠的相对侧形成氮化物间隔物; 在第二多晶硅栅叠层的相对侧形成深源极/漏极区; 在每个多晶硅栅极堆叠周围形成厚度小于距离基板的上表面的多晶硅栅叠层高度的厚度的填充层; 将氮化物间隔物的上部分除去湿间隙填充层的高度，然后除去湿间隙填充层; 并执行深源极/漏极区和硅帽的硅化。

公开(公告)号：US20160064286A1

公开(公告)日：2016-03-03

申请号：US14476031

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Gabriela Dilliway ,  Bo Bai ,  Peter Javorka ,  Dina H. Triyoso

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092

Abstract: Methods for fabricating integrated circuits and components thereof are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit is provided. The method includes providing a semiconductor substrate with a first gate structure and a second gate structure and a shallow trench isolation region outside of the first and second gate structures, depositing a mask on the first gate structure, and depositing a protection layer on the shallow trench isolation region to embed a STI protective cap.

Abstract translation: 提供了制造集成电路及其部件的方法。 根据示例性实施例，提供了一种用于制造集成电路的方法。 该方法包括在第一和第二栅极结构之外提供具有第一栅极结构和第二栅极结构以及浅沟槽隔离区域的半导体衬底，在第一栅极结构上沉积掩模，以及在浅沟槽上沉积保护层 隔离区域嵌入STI保护帽。

公开(公告)号：US09224655B2

公开(公告)日：2015-12-29

申请号：US13792540

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Ralf Richter ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/311 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes the steps of forming a masking layer that covers a P-type transistor and exposes at least a gate cap layer of an N-type transistor, performing a first etching process through the masking layer to remove a portion of the gate cap of the N-type transistor so as to thereby define a reduced thickness gate cap layer for the N-type transistor, removing the masking layer, and performing a common second etching process on the P-type transistor and the N-type transistor that removes a gate cap layer of the P-type transistor and the reduced thickness gate cap of the N-type transistor.

Abstract translation: 本文公开的一种说明性方法包括以下步骤：形成覆盖P型晶体管并暴露N型晶体管的至少栅极帽层的掩模层，通过掩模层执行第一蚀刻工艺以去除部分 N型晶体管的栅极帽，从而限定了用于N型晶体管的减小厚度的栅极盖层，去除掩模层，并对P型晶体管和N型晶体管执行公共的第二蚀刻工艺 其去除了N型晶体管的P型晶体管的栅极盖层和减小厚度的栅极盖。

公开(公告)号：US08877582B2

公开(公告)日：2014-11-04

申请号：US13771294

申请日：2013-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Stefan Flachowsky ,  Nicolas Sassiat

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/7847

Abstract: One method herein includes forming a gate structure above an active area of a semiconductor substrate, forming sidewall spacer structures adjacent the gate structure, forming a masking layer that allows implantation of ions into the gate electrode but not into areas of the active region where source/drain regions for the transistor will be formed, performing a gate ion implantation process to form a gate ion implant region in the gate electrode and performing an anneal process. An N-type transistor including sidewall spacer structures positioned adjacent a gate structure, a plurality of source/drain regions for the transistor and a gate implant region positioned in a gate electrode, wherein the gate implant region is comprised of ions of phosphorous, arsenic or an implant material with an atomic size that is equal to or greater than the atomic size of phosphorous at a concentration level that falls within the range of 5e18-5e21 ions/cm3.

Abstract translation: 这里的一种方法包括在半导体衬底的有源区上方形成栅极结构，形成与栅极结构相邻的侧壁间隔结构，形成允许将离子注入栅电极但不进入有源区的源的/ 将形成用于晶体管的漏极区域，执行栅极离子注入工艺以在栅极电极中形成栅极离子注入区域并执行退火工艺。 一种N型晶体管，其包括邻近栅极结构定位的侧壁间隔结构，用于晶体管的多个源极/漏极区域和位于栅极电极中的栅极注入区域，其中栅极注入区域由磷，砷或 原子尺寸等于或大于磷离子浓度在5e18-5e21离子/ cm3范围内的原子尺寸的植入材料。

公开(公告)号：US20140256137A1

公开(公告)日：2014-09-11

申请号：US13793082

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ralf Richter ,  Jan Hoentschel ,  Sven Beyer ,  Peter Javorka

IPC: H01L21/265

CPC classification number: H01L21/265 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: A method includes providing a semiconductor structure including a substrate and a transistor element. A layer of a spacer material is deposited over the substrate and the gate structure, wherein the deposited layer of spacer material has an intrinsic stress. Ions are implanted into the layer of spacer material. After the deposition of the layer of spacer material and the implantation of ions into the layer of spacer material, a sidewall spacer is formed at sidewalls of the gate structure from the layer of spacer material.

Abstract translation: 一种方法包括提供包括衬底和晶体管元件的半导体结构。 在衬底和栅极结构上沉积间隔材料层，其中间隔物材料的沉积层具有固有应力。 离子被植入到间隔物材料层中。 在间隔物材料层沉积并将离子注入到间隔物材料层中之后，在间隔物材料层的栅极结构的侧壁处形成侧壁间隔物。