公开(公告)号：US07737039B2

公开(公告)日：2010-06-15

申请号：US11933664

申请日：2007-11-01

申请人： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

发明人： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

IPC分类号： H01L21/311

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

摘要翻译： 公开了诸如涉及增加集成电路中的隔离特征的密度的方法。 还公开了与该方法相关联的结构。 在一个或多个实施例中，触头在其它结构（例如导电互连）的间距上形成。 互连可以由间距倍增形成。 为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。 可选择定义的材料中的特征被修剪到期望的尺寸。 间隔材料被毯子沉积在可选择定义的材料中的特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。 去除可选择定义的材料以留下由间隔物材料限定的掩模。 由间隔物材料限定的图案可以转移到基底上，以形成间距接触。 在一些实施例中，上电触点可用于电接触衬底中的导电互连。

公开(公告)号：US10515801B2

公开(公告)日：2019-12-24

申请号：US12908206

申请日：2010-10-20

申请人： Gurtej Sandhu

发明人： Gurtej Sandhu

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

摘要： Self-assembling materials, such as block copolymers, are used as mandrels for pitch multiplication. The copolymers are deposited over a substrate and directed to self-assemble into a desired pattern. One of the blocks forming the block copolymers is selectively removed. The remaining blocks are used as mandrels for pitch multiplication. Spacer material is blanket deposited over the blocks. The spacer material is subjected to a spacer etch to form spacers on sidewalls of the mandrels. The mandrels are selectively removed to leave free-standing spacers. The spacers may be used as pitch-multiplied mask features to define a pattern in an underlying substrate.

公开(公告)号：US09196753B2

公开(公告)日：2015-11-24

申请号：US13089648

申请日：2011-04-19

申请人： D. V. Nirmal Ramaswamy ,  Gurtej Sandhu

发明人： D. V. Nirmal Ramaswamy ,  Gurtej Sandhu

IPC分类号： H01L27/108 ,  H01L29/872 ,  H01L27/28 ,  H01L45/00 ,  H01L27/102 ,  H01L29/885 ,  H01L27/22 ,  H01L27/24 ,  G11C11/56 ,  G11C13/00

CPC分类号： H01L29/872 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/71 ,  H01L27/1021 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/285 ,  H01L29/885 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first electrode, where the semiconductive stack can have a thickness of about 700 angstroms (Å) or less. Each of the at least one semiconductive material can have an associated band gap of about 4 electron volts (eV) or less and a second electrode can be formed on the semiconductive stack.

摘要翻译： 为选择装置提供方法，装置和系统，所述选择装置可以包括形成在第一电极上的至少一个半导体材料的半导体叠层，其中半导体叠层可以具有约700埃（或更小）的厚度。 所述至少一个半导体材料中的每一个可以具有约4电子伏（eV）或更小的相关带隙，并且可以在半导体叠层上形成第二电极。

公开(公告)号：US08946907B2

公开(公告)日：2015-02-03

申请号：US13526225

申请日：2012-06-18

申请人： Gurtej Sandhu

发明人： Gurtej Sandhu

IPC分类号： H01L23/52 ,  H01L21/311 ,  H01L21/033

CPC分类号： H01L23/5226 ,  H01L21/0337 ,  H01L21/31144 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for creating structures in a semiconductor assembly is provided. The method includes etching apertures into a dielectric layer and applying a polymer layer over the dielectric layer. The polymer layer is applied uniformly and fills the apertures at different rates depending on the geometry of the apertures, or on the presence or absence of growth accelerating material. The polymer creates spacers for the etching of additional structure in between the spacers. The method is capable of achieving structures smaller than current lithography techniques.

摘要翻译： 提供了一种用于在半导体组件中产生结构的方法。 该方法包括将孔蚀刻到电介质层中，并在该介电层上施加聚合物层。 均匀地施加聚合物层，并根据孔的几何形状，或者存在或不存在生长促进材料，以不同的速率填充孔。 该聚合物产生用于蚀刻间隔物之间​​的附加结构的间隔物。 该方法能够实现比当前光刻技术更小的结构。

公开(公告)号：US08796661B2

公开(公告)日：2014-08-05

申请号：US12917348

申请日：2010-11-01

申请人： Nirmal Ramaswamy ,  Gurtej Sandhu

发明人： Nirmal Ramaswamy ,  Gurtej Sandhu

IPC分类号： H01L47/00 ,  H01L21/06 ,  H01L21/20

CPC分类号： H01L45/085 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/1273 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1683

摘要： A method of forming a nonvolatile memory cell includes forming a first electrode having a first current conductive material and a circumferentially self-aligned second current conductive material projecting elevationally outward from the first current conductive material. The second current conductive material is different in composition from the first current conductive material. A programmable region is formed over the first current conductive material and over the projecting second current conductive material of the first electrode. A second electrode is formed over the programmable region. In one embodiment, the programmable region is ion conductive material, and at least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Other method and structural aspects are disclosed.

摘要翻译： 形成非易失性存储单元的方法包括形成具有第一电流导电材料的第一电极和从第一电流导电材料向外突出的周向自对准的第二导电材料。 第二电流导电材料的组成不同于第一电流导电材料。 可编程区域形成在第一电流导电材料之上并且在第一电极的突出的第二电流导电材料之上。 在可编程区域上形成第二电极。 在一个实施例中，可编程区域是离子传导材料，并且第一和第二电极中的至少一个电极具有直接抵靠离子导电材料的电化学活性表面。 公开了其它方法和结构方面。

公开(公告)号：US20130188903A1

公开(公告)日：2013-07-25

申请号：US13354767

申请日：2012-01-20

申请人： Gurtej Sandhu ,  Roy Meade

发明人： Gurtej Sandhu ,  Roy Meade

IPC分类号： G02B6/12 ,  H01L21/02

CPC分类号： G02B6/12 ,  B82Y20/00 ,  G02B6/122 ,  G02B6/1223 ,  G02B6/1225 ,  G02B6/13 ,  G02B2006/121 ,  H01L2933/0083

摘要： A photonic device and methods of formation that provide an area providing reduced optical coupling between a substrate and an inner core of the photonic device are described. The area is formed using holes in the inner core and an outer cladding. The holes may be filled with materials which provide a photonic crystal. Thus, the photonic device may function as a waveguide and as a photonic crystal.

摘要翻译： 描述了提供在光子器件的衬底和内核之间提供减小的光学耦合的区域的光子器件和形成方法。 该区域由内芯和外包层中的孔形成。 孔可以填充提供光子晶体的材料。 因此，光子器件可以用作波导和光子晶体。

公开(公告)号：US08450154B2

公开(公告)日：2013-05-28

申请号：US13087050

申请日：2011-04-14

申请人： Jun Liu ,  Gurtej Sandhu

发明人： Jun Liu ,  Gurtej Sandhu

IPC分类号： H01L21/82

CPC分类号： H01L45/145 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1683

摘要： Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming a substoichiometric oxide over the first conductive element, forming a second conductive element over the substoichiometric oxide, and oxidizing edges of the substoichiometric oxide by subjecting the substoichiometric oxide to an oxidizing environment to define a controlled oxygen vacancy conduction path near a center of the oxide.

摘要翻译： 与基于氧化物的存储器相关联的方法，装置和系统可以包括形成基于氧化物的存储器单元的方法。 形成基于氧化物的存储单元可以包括形成第一导电元件，在第一导电元件上形成亚化学计量氧化物，在亚化学计量氧化物上形成第二导电元件，以及通过使亚化学计量氧化物氧化成氧化环境来氧化亚化学计量氧化物的边缘 以限定氧化物中心附近的受控氧空位传导路径。

公开(公告)号：US08358531B2

公开(公告)日：2013-01-22

申请号：US13357527

申请日：2012-01-24

申请人： Jun Liu ,  Gurtej Sandhu

发明人： Jun Liu ,  Gurtej Sandhu

IPC分类号： G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  G11C11/02

CPC分类号： G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1695 ,  H01L43/02

摘要： Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.

摘要翻译： 配置为单向编程的自旋扭矩传递磁性随机存取存储器件以及编程这种器件的方法。 这些装置包括具有两个钉扎层和其间的自由层的存储单元。 通过利用两个固定层，分别从两个固定层中的每一个自由层上的自旋转矩效应允许以单向电流编程存储器单元。

公开(公告)号：US20120326242A1

公开(公告)日：2012-12-27

申请号：US13605511

申请日：2012-09-06

申请人： Gurtej Sandhu ,  John K. Zahurak ,  Jay Parks

发明人： Gurtej Sandhu ,  John K. Zahurak ,  Jay Parks

IPC分类号： H01L27/088

CPC分类号： H01L27/2454 ,  H01L27/2463 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1233

摘要： A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to one of a plurality of second silicide layers on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.

公开(公告)号：US20120261638A1

公开(公告)日：2012-10-18

申请号：US13086321

申请日：2011-04-13

申请人： Scott E. Sills ,  Gurtej Sandhu

发明人： Scott E. Sills ,  Gurtej Sandhu

IPC分类号： H01L45/00

CPC分类号： H01L45/1226 ,  H01L27/2463 ,  H01L27/249 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/122 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： This disclosure provides embodiments for the formation of vertical memory cell structures that may be implemented in RRAM devices. In one embodiment, memory cell area may be increased by varying word line height and/or word line interface surface characteristics to ensure the creation of a grain boundary that is suitable for formation of conductive pathways through an active layer of an RRAM memory cell. This may maintain continuum behavior while reducing random cell-to-cell variability that is often encountered at nanoscopic scales. In another embodiment, such vertical memory cell structures may be formed in multiple-tiers to define a three-dimensional RRAM memory array. Further embodiments also provide a spacer pitch-doubled RRAM memory array that integrates vertical memory cell structures.

摘要翻译： 本公开提供了可以在RRAM设备中实现的垂直存储器单元结构的形成的实施例。 在一个实施例中，可以通过改变字线高度和/或字线界面表面特性来增加存储器单元面积，以确保产生适于通过RRAM存储器单元的有源层形成导电路径的晶界。 这可以保持连续体行为，同时减少在纳米尺度上经常遇到的随机细胞间变异性。 在另一实施例中，这样的垂直存储单元结构可以以多层形成以定义三维RRAM存储器阵列。 另外的实施例还提供了一种集成垂直存储单元结构的间隔物间距加倍的RRAM存储器阵列。