公开(公告)号：US20160092172A1

公开(公告)日：2016-03-31

申请号：US14497777

申请日：2014-09-26

申请人： Karthik Sarpatwari ,  Hongmei Wang ,  Sanjay Rangan

发明人： Karthik Sarpatwari ,  Hongmei Wang ,  Sanjay Rangan

IPC分类号： G06F7/58

CPC分类号： G06F21/44 ,  G06F7/58 ,  G06F7/588 ,  G09C1/00 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

摘要： Devices and systems operable to generate random numbers are disclosed and described. Such include an array of phase change material cells electrically coupled to circuitry configured to initially set all cells in the array to a high state, send a programming pulse through the array having a current sufficient to randomly set each cell to either the high state or a low state to generate a random distribution of cell states across the array, and to read the random distribution of cell states out of the array.

摘要翻译： 公开和描述了可操作以产生随机数的装置和系统。 这样包括电耦合到被配置为初始地将阵列中的所有单元设置为高状态的电路的相变材料单元的阵列，通过阵列发送编程脉冲，该阵列具有足以将每个单元随机地设置为高状态或 低状态以在阵列上产生单元状态的随机分布，并且读取阵列外的单元状态的随机分布。

公开(公告)号：US08707018B1

公开(公告)日：2014-04-22

申请号：US13170827

申请日：2011-06-28

申请人： Richard A. Hooker ,  Ashok Ramakrishnan ,  Hongmei Wang ,  Joseph A. Leslie

发明人： Richard A. Hooker ,  Ashok Ramakrishnan ,  Hongmei Wang ,  Joseph A. Leslie

IPC分类号： G06F9/00 ,  G06F9/24 ,  G06F1/24

CPC分类号： G06F9/4411

摘要： A method is used in managing initialization of file systems. Activity of file systems is monitored. The file systems include a first and second set of file systems. Based on activity of the file systems, the first set of file systems is associated with a first section of a boot configuration file and the second set of file systems is associated with a second section of the boot configuration file. The first and second sets of file systems are initialized for providing access to the first and second sets of file systems. Access to the first set of file systems is provided before initializing the second set of file systems.

摘要翻译： 一种方法用于管理文件系统的初始化。 监视文件系统的活动。 文件系统包括第一和第二组文件系统。 基于文件系统的活动，第一组文件系统与引导配置文件的第一部分相关联，并且第二组文件系统与引导配置文件的第二部分相关联。 第一和第二组文件系统被初始化以提供对第一和第二组文件系统的访问。 在初始化第二组文件系统之前，提供对第一组文件系统的访问。

公开(公告)号：US20120205616A1

公开(公告)日：2012-08-16

申请号：US13028055

申请日：2011-02-15

申请人： Jianping Zhang ,  Hongmei Wang ,  Chunhui Yan

发明人： Jianping Zhang ,  Hongmei Wang ,  Chunhui Yan

IPC分类号： H01L33/06 ,  B82Y40/00 ,  B82Y99/00

CPC分类号： H01L33/0075 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/02458 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02601 ,  H01L21/0262 ,  H01L21/02631 ,  H01L33/007 ,  H01L33/025 ,  H01L33/06 ,  H01L33/12

摘要： A method for reducing dislocations or other defects in a light emitting device, such as light emitting diode (LED), by in-situ introducing nanoparticles into at least one of a defect-controlling layer, an n-type layer, a p-type layer, and a quantum well of the light emitting device. A light emitting device is provided, and nanoparticles are dispensed in-situ in at least one of a defect-controlling layer, an n-type layer, a p-type layer, and a quantum well of the light emitting device.

摘要翻译： 通过将纳米颗粒原位引入到缺陷控制层，n型层，p型中的至少一种中，减少诸如发光二极管（LED）的发光器件中的位错或其它缺陷的方法 层和发光器件的量子阱。 提供了一种发光器件，并且纳米颗粒在发光器件的缺陷控制层，n型层，p型层和量子阱中的至少一个中被原位分配。

公开(公告)号：US07935602B2

公开(公告)日：2011-05-03

申请号：US11168861

申请日：2005-06-28

申请人： Hongmei Wang ,  Fred D. Fishburn ,  Janos Fucsko ,  T. Earl Allen ,  Richard H. Lane ,  Robert J. Hanson ,  Kevin R. Shea

发明人： Hongmei Wang ,  Fred D. Fishburn ,  Janos Fucsko ,  T. Earl Allen ,  Richard H. Lane ,  Robert J. Hanson ,  Kevin R. Shea

IPC分类号： H01L21/336 ,  H01L21/311 ,  H01L21/302

CPC分类号： H01L21/76232

摘要： The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the opening can be protected with a liner while a lower periphery is unlined. The unlined portion can then be etched to form a widened region of the opening. Subsequently, the opening can be filled with insulative material to form an isolation region. Transistor devices can then be formed on opposing sides of the isolation region, and electrically isolated from one another with the isolation region. The invention also includes semiconductor constructions containing an electrically insulative isolation structure extending into a semiconductor material, with the structure having a bulbous bottom region and a stem region extending upwardly from the bottom region to a surface of the semiconductor material.

摘要翻译： 本发明包括形成隔离区域的方法。 可以形成开口以延伸到半导体材料中，并且可以用衬垫保护开口的上周边，而下边缘是无衬里的。 然后可以对无衬里部分进行蚀刻以形成开口的加宽区域。 随后，开口可以用绝缘材料填充以形成隔离区域。 晶体管器件然后可以形成在隔离区域的相对侧上，并且与隔离区域彼此电隔离。 本发明还包括包含延伸到半导体材料中的电绝缘隔离结构的半导体结构，其结构具有球形底部区域和从底部区域向上延伸到半导体材料表面的杆区域。

公开(公告)号：US07667234B2

公开(公告)日：2010-02-23

申请号：US11811502

申请日：2007-06-11

申请人： Hongmei Wang ,  Chandra Mouli ,  Luan Tran

发明人： Hongmei Wang ,  Chandra Mouli ,  Luan Tran

IPC分类号： H01L29/04

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/41758 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7854 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

摘要： A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to form word lines that intersect the active area lines at the angled segments.

摘要翻译： 具有减小的单元尺寸并且具有增加的沟道宽度的晶体管的存储器阵列。 更具体地，在衬底中形成支柱，使得侧壁被暴露。 支柱的侧壁和柱的顶表面被栅极氧化物和多晶硅层覆盖以形成通过柱的通道。 通过通道的电流通道大约等于柱的高度加上柱的宽度的两倍。 支柱被图案化以形成具有成角度段的非线性有源面积线。 将多晶硅层图案化以形成与成角度段的有源区域线相交的字线。

公开(公告)号：US07638392B2

公开(公告)日：2009-12-29

申请号：US11406862

申请日：2006-04-18

申请人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

发明人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

IPC分类号： H01L21/8242

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823412 ,  H01L27/0811 ,  H01L27/088 ,  H01L29/66537 ,  H01L29/7833

摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

摘要翻译： 本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。 本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为 在介电材料的下方并与导电掺杂的扩散区相邻。 形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。 当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

公开(公告)号：US07517743B2

公开(公告)日：2009-04-14

申请号：US11588274

申请日：2006-10-27

申请人： Hongmei Wang ,  John K. Zahurak

发明人： Hongmei Wang ,  John K. Zahurak

IPC分类号： H01L21/336

CPC分类号： H01L29/4908 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/78621

摘要： A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.

摘要翻译： 公开了一种完全耗尽（FD）的绝缘体上硅（SOI）MOSFET存取晶体管，其包括与源/漏区的导电类型相反的导电类型的栅电极和制造方法。

公开(公告)号：US07465999B2

公开(公告)日：2008-12-16

申请号：US10303696

申请日：2002-11-26

申请人： Hongmei Wang ,  John K. Zahurak

发明人： Hongmei Wang ,  John K. Zahurak

IPC分类号： H01L27/105 ,  H01L27/12

CPC分类号： H01L29/4908 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/78621

摘要： A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed.

摘要翻译： 公开了一种完全耗尽（FD）的绝缘体上硅（SOI）MOSFET存取晶体管，其包括与源/漏区的导电类型相反的导电类型的栅电极和制造方法。

公开(公告)号：US07332767B2

公开(公告)日：2008-02-19

申请号：US11286670

申请日：2005-11-23

申请人： Hongmei Wang ,  Chandra Mouli ,  Luan Tran

发明人： Hongmei Wang ,  Chandra Mouli ,  Luan Tran

IPC分类号： H01L29/788

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/41758 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7854 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

摘要： A memory device having decreased cell size and having transistors with increased channel widths. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a conductive layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The conductive layer is patterned to from word lines that intersect the active area lines at the angled segments.

摘要翻译： 具有减小的单元尺寸并且具有增加的沟道宽度的晶体管的存储器件。 支柱的侧壁和柱的顶表面被栅极氧化物和导电层覆盖以形成通过柱的通道。 通过通道的电流通道大约等于柱的高度加上柱的宽度的两倍。 支柱被图案化以形成具有成角度段的非线性有源面积线。 导电层被图案化以形成与成角度段的有源区域线相交的字线。

公开(公告)号：US20070241395A1

公开(公告)日：2007-10-18

申请号：US11811502

申请日：2007-06-11

申请人： Hongmei Wang ,  Chandra Mouli ,  Luan Tran

发明人： Hongmei Wang ,  Chandra Mouli ,  Luan Tran

IPC分类号： H01L29/94

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/41758 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7854 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

摘要： A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to form word lines that intersect the active area lines at the angled segments.