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    Nonvolatile memory device and method of reading information from the same
    41.
    发明申请
    Nonvolatile memory device and method of reading information from the same 失效
    非易失性存储器件和从其读取信息的方法

    公开(公告)号：US20080101128A1

    公开(公告)日：2008-05-01

    申请号：US11605225

    申请日：2006-11-29

    申请人： Ho-jung Kim

    发明人： Ho-jung Kim

    IPC分类号： G11C11/34

    CPC分类号： G11C16/26 ,  G11C16/24

    摘要： A nonvolatile memory device includes a memory cell array and a voltage controller. The memory cell array includes a plurality of memory blocks each including a plurality of cell strings, where each of the cell strings includes a first selection transistor, a second selection transistor, and at least one memory cell transistor connected in series between the first and second selection transistors. The voltage controller applies a first selection voltage to first selection lines connected to the first selection transistors, a second selection voltage to second selection lines connected to the second selection transistors, and a word line voltage to word lines connected to the memory cell transistors, in response to a plurality of block selection signals corresponding to the memory blocks. The voltage controller precharges the second selection lines to a precharge voltage by applying the second selection line voltage to the second selection lines in a standby state, where the second selection line voltage is equal to the precharge voltage.

    摘要翻译： 非易失性存储器件包括存储单元阵列和电压控制器。 存储单元阵列包括多个存储块，每个存储块包括多个单元串，其中每个单元串包括第一选择晶体管，第二选择晶体管和串联连接在第一和第二单元串之间的至少一个存储单元晶体管 选择晶体管。 电压控制器对连接到第一选择晶体管的第一选择线，连接到第二选择晶体管的第二选择线的第二选择电压和连接到存储单元晶体管的字线的字线电压施加第一选择电压， 响应于对应于存储块的多个块选择信号。 电压控制器通过在第二选择线电压等于预充电电压的待机状态下将第二选择线电压施加到第二选择线，将第二选择线预充电到预充电电压。

    Oscillator reducing clock signal variations due to variations in voltage or temperature
    42.
    发明申请
    Oscillator reducing clock signal variations due to variations in voltage or temperature 有权
    振荡器减少由于电压或温度变化引起的时钟信号变化

    公开(公告)号：US20070285186A1

    公开(公告)日：2007-12-13

    申请号：US11790012

    申请日：2007-04-23

    申请人： Ho-jung Kim

    发明人： Ho-jung Kim

    IPC分类号： H03L1/00

    CPC分类号： H03L1/00 ,  H03K3/011 ,  H03K3/354

    摘要： Provided is an oscillator including a logic signal generator and a clock generator. The logic signal generator generates a first logic signal and a second logic signal that have the same period but have different logic level transition timing. The clock generator generates a clock signal in response to the first logic signal and the second logic signal. The oscillator compensates for an amount of variation of a reference current using a compensation current, thereby maintaining a constant period of the clock signal.

    摘要翻译： 提供了包括逻辑信号发生器和时钟发生器的振荡器。 逻辑信号发生器产生具有相同周期但具有不同逻辑电平转换时序的第一逻辑信号和第二逻辑信号。 时钟发生器响应于第一逻辑信号和第二逻辑信号产生时钟信号。 振荡器使用补偿电流来补偿参考电流的变化量，从而保持时钟信号的恒定周期。

    Microprocessor chip, data center, and computing system
    43.
    发明授权
    Microprocessor chip, data center, and computing system 有权
    微处理器芯片，数据中心和计算系统

    公开(公告)号：US09059808B2

    公开(公告)日：2015-06-16

    申请号：US13611839

    申请日：2012-09-12

    申请人： Ho-jung Kim ,  Young-soo Park

    发明人： Ho-jung Kim ,  Young-soo Park

    IPC分类号： H04B10/00 ,  H04B10/80

    CPC分类号： H04B10/801

    摘要： A microprocessor chip includes a plurality of processors; at least one first optical input/output unit configured to receive optical signals from an external device and transmit optical signals to the external device; and an optical system bus that is connected between the plurality of processors and the at least one first optical input/output unit.

    摘要翻译： 微处理器芯片包括多个处理器; 至少一个第一光输入/输出单元，被配置为从外部设备接收光信号并将光信号传输到所述外部设备; 以及连接在所述多个处理器与所述至少一个第一光学输入/输出单元之间的光学系统总线。

    Stacked memory devices
    45.
    发明授权
    Stacked memory devices 有权
    堆叠式存储器件

    公开(公告)号：US08611121B2

    公开(公告)日：2013-12-17

    申请号：US12662785

    申请日：2010-05-04

    申请人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

    发明人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

    IPC分类号： G11C5/02

    CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C2213/71 ,  G11C2213/72

    摘要： A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups.

    摘要翻译： 层叠的存储器件可以包括衬底，顺序地堆叠在衬底上的多个存储器组，每个存储器组包括至少一个存储器层，多个X译码器层，所述多个X译码器层中的至少一个是 设置在所述多个存储器组中的每个相邻的两个存储器组之间，以及与所述多个X解码器层交替布置的多个Y译码器层，所述多个Y译码器层中的至少一个设置在每个相邻的两个存储器组之间 的多个存储器组。

    Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit
    46.
    发明授权
    Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit 有权
    非易失性逻辑电路，包括非易失性逻辑电路的集成电路和操作集成电路的方法

    公开(公告)号：US08509004B2

    公开(公告)日：2013-08-13

    申请号：US12801502

    申请日：2010-06-11

    申请人： Ho-jung Kim ,  Jai-kwang Shin ,  Kwang-seok Kim ,  Kee-won Kim

    发明人： Ho-jung Kim ,  Jai-kwang Shin ,  Kwang-seok Kim ,  Kee-won Kim

    IPC分类号： G11C7/10

    CPC分类号： H03K19/1733 ,  G11C14/0054 ,  G11C14/0081 ,  G11C14/009 ,  H03K3/356008

    摘要： A nonvolatile logic circuit includes a latch unit including a pair of first and second latch nodes; and a pair of first and second nonvolatile memory cells electrically connected to the first and second of latch nodes, respectively. A write operation is performed on the first and second nonvolatile memory cells according to a direction of a current flowing through the first and second nonvolatile memory cells when a write enable signal is activated. The direction of flow of current determined based on data on the respective first and second latch nodes, and a logic value written on the first nonvolatile memory cells is different from a logic value written on the second nonvolatile memory cell.

    摘要翻译： 非易失性逻辑电路包括：锁存单元，包括一对第一和第二锁存节点; 以及分别电连接到第一和第二锁存节点的一对第一和第二非易失性存储单元。 当写入使能信号被激活时，根据流过第一和第二非易失性存储器单元的电流的方向在第一和第二非易失性存储器单元上执行写入操作。 基于相应的第一和第二锁存节点上的数据确定的电流的流动方向和写在第一非易失性存储器单元上的逻辑值与写入第二非易失性存储单元的逻辑值不同。

    Semiconductor device
    47.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08508194B2

    公开(公告)日：2013-08-13

    申请号：US12923857

    申请日：2010-10-12

    申请人： Ho-jung Kim ,  Jong-seob Kim ,  Jai-kwang Shin ,  Jae-joon Oh ,  Ki-ha Hong ,  In-jun Hwang ,  Hyuk-soon Choi

    发明人： Ho-jung Kim ,  Jong-seob Kim ,  Jai-kwang Shin ,  Jae-joon Oh ,  Ki-ha Hong ,  In-jun Hwang ,  Hyuk-soon Choi

    IPC分类号： G05F1/10

    CPC分类号： H03K17/6871 ,  H02M1/08 ,  H02M3/158 ,  H02M3/337 ,  H02M2001/0074 ,  H03K2217/0081

    摘要： Provided is a semiconductor device that may include a switching device having a negative threshold voltage, and a driving unit between a power terminal and a ground terminal and providing a driving voltage for driving the switching device. The switching device may be connected to a virtual ground node having a virtual ground voltage that is greater than a ground voltage supplied from the ground terminal and may be turned on when a difference between the driving voltage and the virtual ground voltage is greater than the negative threshold voltage.

    摘要翻译： 提供一种半导体器件，其可以包括具有负阈值电压的开关器件，以及电源端子和接地端子之间的驱动单元，并且提供用于驱动开关器件的驱动电压。 开关器件可以连接到具有大于从接地端子提供的接地电压的虚拟接地电压的虚拟接地节点，并且当驱动电压和虚拟接地电压之间的差大于负值时，可以导通 阈值电压。

    Stacked memory device including a pre-decoder/pre-driver sandwiched between a plurality of inter-decoders/inter-drivers
    48.
    发明授权
    Stacked memory device including a pre-decoder/pre-driver sandwiched between a plurality of inter-decoders/inter-drivers 有权
    堆叠存储器件包括夹在多个解码器/驱动器之间的预解码器/预驱动器

    公开(公告)号：US08054665B2

    公开(公告)日：2011-11-08

    申请号：US12654645

    申请日：2009-12-28

    申请人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

    发明人： Seung-eon Ahn ,  Ho-jung Kim ,  Chul-woo Park ,  Sang-beom Kang ,  Hyun-ho Choi

    IPC分类号： G11C5/02

    CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C13/0023 ,  G11C2213/71 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/49 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-decoders electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-decoder electrically connected to the plurality of inter-decoders and disposed between the plurality of inter-decoders. A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-drivers electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-driver electrically connected to the plurality of inter-drivers, and disposed between the plurality of inter-drivers.

    摘要翻译： 层叠的存储器件可以包括衬底，堆叠在衬底上和衬底上并被分成多个组的多个存储器层，多个解码器电连接到多个存储器层并且布置在多个存储器层中的相应的一个 所述多个组以及至少一个预解码器电连接到所述多个解码器并且设置在所述多个解码器之间。 层叠的存储器件可以包括衬底，堆叠在衬底上和衬底上并被分成多个组的多个存储器层，多个驱动器电连接到多个存储器层并且被布置在多个存储器层中的相应的一个 所述多个组，以及电连接到所述多个驱动器之间的至少一个预驱动器，并且设置在所述多个驱动器之间。