公开(公告)号：US20240413212A1

公开(公告)日：2024-12-12

申请号：US18808702

申请日：2024-08-19

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Jphn Twynam

IPC: H01L29/40 ,  H01L21/765 ,  H01L23/29 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778

Abstract: In an embodiment, a Group III nitride-based transistor device includes a first passivation layer arranged on a first major surface of a Group III nitride-based layer, a second passivation layer arranged on the first passivation layer, a source ohmic contact, a drain ohmic contact and a gate positioned on the first major surface of a Group III nitride-based layer, and a field plate, the field plate being laterally arranged between and spaced apart from the gate and the drain ohmic contact.

公开(公告)号：US11581418B2

公开(公告)日：2023-02-14

申请号：US16894223

申请日：2020-06-05

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Rudolf Berger ,  Helmut Brech ,  Olaf Storbeck ,  Haifeng Sun ,  John Twynam

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/268 ,  H01L23/29 ,  H01L23/31 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/778

Abstract: A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.

公开(公告)号：US11342451B2

公开(公告)日：2022-05-24

申请号：US16697490

申请日：2019-11-27

Applicant: Infineon Technologies AG

Inventor： John Twynam ,  Albert Birner ,  Helmut Brech

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/265 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207 ,  H01L29/32 ,  H01L29/66

Abstract: A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary.

公开(公告)号：US10720359B2

公开(公告)日：2020-07-21

申请号：US15856742

申请日：2017-12-28

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/288

Abstract: In an embodiment, a substrate includes semiconductor material and a conductive via. The conductive via includes a via in the substrate, a conductive plug filling a first portion of the via, and a conductive liner layer that lines side walls of a second portion of the via and is electrically coupled to the conductive plug. The conductive liner layer and the conductive plug have different microstructures.

公开(公告)号：US10672686B2

公开(公告)日：2020-06-02

申请号：US16535237

申请日：2019-08-08

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Matthias Zigldrum

IPC: H01L21/288 ,  H01L21/768 ,  H01L23/48 ,  H01L29/417 ,  H01L29/78 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

Abstract: A method of forming a conductive through substrate via includes forming an opening in a first surface of a semiconductor substrate comprising a LDMOS transistor structure in the first surface, forming a first conductive layer in a first portion of the opening in the semiconductor substrate using first deposition parameters such that the first conductive layer fills the opening in the first portion, and forming a second conductive layer on the first conductive layer in a second portion of the opening using second deposition parameters such that the second conductive layer bounds a gap in the second portion.

公开(公告)号：US20200168709A1

公开(公告)日：2020-05-28

申请号：US16694070

申请日：2019-11-25

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Jan Ropohl

IPC: H01L29/20 ,  H01L29/45 ,  H01L21/283 ,  H01L29/40

Abstract: In an embodiment, a Group III nitride device includes a multilayer Group III nitride structure and a first ohmic contact arranged on and forming an ohmic contact to the multilayer Group III nitride device structure. The first ohmic contact includes a base portion having a conductive surface, the conductive surface including a peripheral portion and a central portion, the peripheral portion and the central portion being substantially coplanar and being of differing composition, a conductive via positioned on the central portion of the conductive surface and a contact pad positioned on the conductive via.

公开(公告)号：US10304789B2

公开(公告)日：2019-05-28

申请号：US15986433

申请日：2018-05-22

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/66 ,  H01L49/02 ,  H01L29/78 ,  H03F3/193 ,  H03F3/21 ,  H01L23/522

Abstract: In an embodiment, a method includes forming a first opening in a front surface of a semiconductor substrate including a LDMOS transistor structure, and covering the first opening with a first layer to form an enclosed cavity defined by material of the semiconductor substrate and the first layer. The material of the first layer lines sidewalls of the enclosed cavity.

公开(公告)号：US20180374921A1

公开(公告)日：2018-12-27

申请号：US16120855

申请日：2018-09-04

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Helmut Brech ,  Simone Lavanga

IPC: H01L29/205 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/304 ,  H01L21/762 ,  H01L29/20 ,  H01L29/10 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/205 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/304 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/76229 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786

Abstract: In an embodiment, a semiconductor wafer includes a substrate wafer having a device surface region surrounded by a peripheral region, one or more mesas including a Group III nitride layer arranged on the device surface region, and an oxide layer arranged on the device surface region and on the peripheral region. The oxide layer has an upper surface that is substantially coplanar with an upper surface of the one or more mesas.

公开(公告)号：US10020270B2

公开(公告)日：2018-07-10

申请号：US15279649

申请日：2016-09-29

Applicant: Infineon Technologies AG

Inventor： Helmut Brech ,  Albert Birner ,  Matthias Zigldrum ,  Michaela Braun ,  Jan Ropohl

IPC: H01L23/66 ,  H01L29/78 ,  H01L23/48 ,  H01L49/02 ,  H01L21/768 ,  H03F3/193 ,  H03F3/21

CPC classification number: H01L23/66 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2223/6683 ,  H03F3/193 ,  H03F3/21 ,  H03F2200/222 ,  H03F2200/411

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate including a front surface, an LDMOS transistor structure in the front surface, a conductive interconnection structure arranged on the front surface, and at least one cavity arranged in the front surface.

公开(公告)号：US10014230B2

公开(公告)日：2018-07-03

申请号：US15352392

申请日：2016-11-15

Applicant: Infineon Technologies AG

Inventor： Albert Birner ,  Tobias Herzig

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/768 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L22/26 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/20 ,  H01L22/30 ,  H01L22/32 ,  H01L23/3107 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an electronic device includes forming a first opening and a second opening in a workpiece. The first opening is deeper than the second opening. The method further includes forming a fill material within the first opening to form part of a through via and forming the fill material within the second opening.