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    Power semiconductor module with current sensor
    41.
    发明授权
    Power semiconductor module with current sensor 有权
    带电流传感器的功率半导体模块

    公开(公告)号：US09370113B2

    公开(公告)日：2016-06-14

    申请号：US14795348

    申请日：2015-07-09

    Applicant: Infineon Technologies AG

    Inventor： Udo Ausserlechner ,  Andreas Grassmann

    IPC: H01L25/07 ,  G01R31/28 ,  H05K5/00 ,  G01R31/26 ,  G01R19/00 ,  H01L23/367 ,  H01L23/473 ,  H01L25/10 ,  H05K1/02 ,  H05K1/18

    CPC classification number: H05K5/0065 ,  G01R19/0092 ,  G01R31/2644 ,  G01R31/2884 ,  H01L23/3675 ,  H01L23/3735 ,  H01L23/473 ,  H01L23/49811 ,  H01L23/62 ,  H01L25/07 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/49171 ,  H05K1/0203 ,  H05K1/0296 ,  H05K1/053 ,  H05K1/181 ,  H05K2201/10151 ,  H05K2201/10287 ,  H05K2201/10416 ,  H01L2924/00014

    Abstract: A power semiconductor module includes a power electronics substrate having a first surface, a second surface opposite the first surface, a first longitudinal side, a second longitudinal side opposite the first longitudinal side, a module frame, which is arranged to enclose the power electronics substrate, at least one power terminal which is arranged at the first longitudinal side and extends through the module frame, a further terminal, which is arranged at the second longitudinal side and extends through the module frame, at least one power semiconductor component which is arranged on the first surface of the power electronics substrate and is electrically connected to at least one power terminal, and at least one current sensor which is designed to measure a current in a power terminal. The at least one current sensor is arranged on the power terminal and has a signal output connected to the further terminal.

    Abstract translation: 功率半导体模块包括电力电子基板，其具有第一表面，与第一表面相对的第二表面，第一纵向侧，与第一纵向侧相对的第二纵向侧，模块框架，其布置成封闭电力电子基板 至少一个功率端子，其布置在第一纵向侧并延伸穿过模块框架;另一个端子，其布置在第二纵向侧并延伸穿过模块框架;至少一个功率半导体部件，其布置在 电力电子基板的第一表面，并且电连接到至少一个电源端子，以及设计成测量电力端子中的电流的至少一个电流传感器。 所述至少一个电流传感器布置在所述电源端子上，并且具有连接到所述另一端子的信号输出。

    POWER SEMICONDUCTOR PACKAGE
    42.
    发明申请
    POWER SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250062290A1

    公开(公告)日：2025-02-20

    申请号：US18934846

    申请日：2024-11-01

    Applicant: Infineon Technologies AG

    Inventor： Ivan Nikitin ,  Thorsten Scharf ,  Marco Bãßler ,  Andreas Grassmann ,  Waldemar Jakobi

    IPC: H01L25/07 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498

    Abstract: A power semiconductor package includes a plurality of first power semiconductor dies attached to a first metallization layer and a plurality of second power semiconductor dies attached to a second metallization layer. A first structured metal frame disposed above the first metallization layer is electrically connected to a load terminal of each first power semiconductor die. A second structured metal frame disposed above the second metallization layer is electrically connected to a load terminal of each second power semiconductor die and to the first metallization layer. A first lead is electrically connected to the second metallization layer. A second lead is electrically connected to the second metallization layer. A third lead interposed between the first and second leads is electrically connected to the first structured metal frame. A fourth lead is electrically connected to the second structured metal frame.

    POWER ELECTRONIC SYSTEM INCLUDING A SEMICONDUCTOR MODULE AND A COOLER AND METHOD FOR FABRICATING THE SAME
    43.
    发明申请
    POWER ELECTRONIC SYSTEM INCLUDING A SEMICONDUCTOR MODULE AND A COOLER AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20240387325A1

    公开(公告)日：2024-11-21

    申请号：US18652146

    申请日：2024-05-01

    Applicant: Infineon Technologies AG

    Inventor： Andreas Grassmann ,  Steffen Hartmann

    IPC: H01L23/473 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

    Abstract: A power electronic system includes a semiconductor module that includes a power electronic substrate having opposite first and second sides, power semiconductor die arranged over the second side of the substrate, and an encapsulation encapsulating the power semiconductor dies. The first side of the power electronic substrate is at least partially exposed from a first side of the encapsulation. The semiconductor module is arranged over an exterior surface of a wall of a cooler configured for fluidic cooling, such that the first side of the power electronic substrate faces the wall. The cooler includes cooling structures arranged on an interior surface of the wall. A first portion of the wall directly below the power electronic substrate has a first wall thickness and a second portion of the wall laterally next to the first portion has a second wall thickness, the first wall thickness being greater than the second wall thickness.

    Fluid-Cooled Package Having Shielding Layer
    45.
    发明申请
    Fluid-Cooled Package Having Shielding Layer 有权

    公开(公告)号：US20220115293A1

    公开(公告)日：2022-04-14

    申请号：US17557168

    申请日：2021-12-21

    Applicant: Infineon Technologies AG

    Inventor： Andreas Grassmann ,  Wolfram Hable ,  Juergen Hoegerl ,  Ivan Nikitin ,  Achim Strass

    IPC: H01L23/42 ,  H01L23/495 ,  H01L23/552 ,  H01L23/373 ,  H01L23/473

    Abstract: A package includes: at least one electronic chip; an encapsulant encapsulating at least part of the at least one electronic chip; a shielding layer on at least part of an external surface of the encapsulant; and a first heat removal body thermally coupled to the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip to a cooling fluid. The encapsulant has a surface portion that extends in a surface region extending laterally directly adjacent to the first heat removal body. The surface portion of the encapsulant delimits part of a cooling cavity configured to guide the cooling fluid. The shielding layer covers the surface portion of the encapsulant. A corresponding electronic device, method of manufacturing the package, method of manufacturing the electronic device, vehicle, and method of using the electronic device are also described.

    COOLING TECHNIQUES FOR SEMICONDUCTOR PACKAGE
    50.
    发明申请
    COOLING TECHNIQUES FOR SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20190318976A1

    公开(公告)日：2019-10-17

    申请号：US16455494

    申请日：2019-06-27

    Applicant: Infineon Technologies AG

    Inventor： Juergen Hoegerl ,  Andreas Grassmann

    IPC: H01L23/367 ,  H01L23/495 ,  H01L23/31 ,  H01L23/473 ,  H01L23/373

    Abstract: In some examples, a device includes a high-side switch, a first high-side conductive element electrically connected to a first load terminal of the high-side switch, and a second high-side conductive element electrically connected to a second load terminal of the high-side switch. The device also includes a layer of cooling material encapsulating the high-side switch, the first high-side conductive element, and the second high-side conductive element. The device further includes a low-side switch, a first low-side conductive element electrically connected to a first load terminal of the low-side switch, and a second low-side conductive element electrically connected to a second load terminal of the low-side switch. The layer of cooling material encapsulates the low-side switch, the first low-side conductive element, and the second low-side conductive element.

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