公开(公告)号：US20170047400A1

公开(公告)日：2017-02-16

申请号：US15333123

申请日：2016-10-24

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Kelin J. KUHN ,  Tahir GHAN! ,  Anand S. MURTHY ,  Mark ARMSTRONG ,  Rafael RIOS ,  Abhijit Jayant PETHE ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/3115 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/0673 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/78696

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract translation: 公开了一种具有多个内部间隔物的纳米线器件和用于形成所述内部间隔物的方法。 在一个实施例中，半导体器件包括设置在衬底上方的纳米线堆叠，纳米线堆叠具有多个垂直堆叠的纳米线，围绕多个纳米线中的每一个缠绕的栅极结构，限定器件的沟道区，栅极 结构，其具有栅极侧壁，在沟道区域的相对侧上的一对源极/漏极区域; 以及位于纳米线堆叠内部的两个相邻纳米线之间的栅极侧壁的一部分上的内部间隔物。 在一个实施例中，内部间隔物通过在与沟道区相邻蚀刻的凹坑中沉积间隔物形成。 在一个实施例中，通过沟道区蚀刻凹坑。 在另一个实施例中，通过源/漏区蚀刻凹坑。

公开(公告)号：US20250113559A1

公开(公告)日：2025-04-03

申请号：US18374600

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Guowei XU ,  Chiao-Ti HUANG ,  Feng ZHANG ,  Robin CHAO ,  Tao CHU ,  Anand S. MURTHY ,  Ting-Hsiang HUNG ,  Chung-Hsun LIN ,  Oleg GOLONZKA ,  Yang ZHANG ,  Chia-Ching LIN

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: Trench contact structures with etch stop layers, and methods of fabricating trench contact structures with etch-stop layers, are described. In an example, an integrated circuit structure includes a fin structure. An epitaxial source or drain structure is on the fin structure. An isolation structure is laterally adjacent to sides of the fin structure. A dielectric layer is on at least a portion of a top surface of the isolation structure and partially surrounds the epitaxial source or drain structure and leaves an exposed portion of the epitaxial source or drain structure. A conductive trench contact structure is on the exposed portion of the epitaxial source or drain structure. The conductive trench contact structure does not extend into the isolation structure.

公开(公告)号：US20240332392A1

公开(公告)日：2024-10-03

申请号：US18737616

申请日：2024-06-07

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Glenn A. GLASS ,  Thomas T. TROEGER ,  Suresh VISHWANATH ,  Jitendra Kumar JHA ,  John F. RICHARDS ,  Anand S. MURTHY ,  Srijit MUKHERJEE

IPC: H01L29/45 ,  H01L21/28 ,  H01L21/285 ,  H01L29/08 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/28088 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7851

Abstract: Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.

公开(公告)号：US20240312996A1

公开(公告)日：2024-09-19

申请号：US18121724

申请日：2023-03-15

Applicant: Intel Corporation

Inventor： Dan S. LAVRIC ,  Shao Ming KOH ,  Anand S. MURTHY ,  Mauro J. KOBRINSKY

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuit structures having uniform grid metal gate and trench contact cut with pyramidal channel structures are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires having a pyramidal profile with a pyramid angle. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The dielectric cut plug structure has a re-entrant profile with a cut angle laterally spaced apart from the pyramid angle of the pyramidal profile of the vertical stack of horizontal nanowires.

公开(公告)号：US20240224536A1

公开(公告)日：2024-07-04

申请号：US18090807

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Wilfred GOMES

IPC: H10B51/30

CPC classification number: H10B51/30

Abstract: Structures having layer select transistors for shared peripherals in memory are described. In an example, an integrated circuit structure includes a memory structure layer including a capacitor array coupled to a plurality of plate lines. A memory transistor layer is beneath the memory structure layer, the memory transistor layer including front end transistors coupled to corresponding capacitors of the capacitor array of the memory structure layer. A select transistor layer is over the memory structure layer, the select transistor layer including backend transistors having a channel composition different than the front end transistors. One or more of the backend transistors is coupled to one or more of the plurality of plate lines of the memory structure layer.

公开(公告)号：US20240222520A1

公开(公告)日：2024-07-04

申请号：US18090822

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Sagar SUTHRAM ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY ,  Pushkar RANADE

IPC: H01L29/786 ,  H01L23/48 ,  H01L27/088 ,  H01L29/06 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L29/78696 ,  H01L23/481 ,  H01L27/0886 ,  H01L29/0673 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: Structures having vertical shared gate high-drive thin film transistors are described. In an example, an integrated circuit structure includes a stack of alternating dielectric layers and metal layers. A trench is through the stack of alternating dielectric layers and metal layers. A semiconductor channel layer is along sides of the trench. A gate dielectric layer is along sides the semiconductor channel layer in the trench. A gate electrode is within sides of the gate dielectric layer.

公开(公告)号：US20240222271A1

公开(公告)日：2024-07-04

申请号：US18090828

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Pushkar RANADE ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY ,  Sagar SUTHRAM

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/528 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Structures having routing across layers of channel structures are described. In an example, an integrated circuit structure includes a first stack of horizontal nanowires along a vertical direction. A second stack of horizontal nanowires is along the vertical direction, the second stack of horizontal nanowires beneath the first stack of horizontal nanowires. A conductive routing layer extends laterally between the first stack of horizontal nanowires and the second stack of horizontal nanowires.

公开(公告)号：US20230420533A1

公开(公告)日：2023-12-28

申请号：US17851960

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Abhishek Anil SHARMA ,  Wilfred GOMES ,  Anand S. MURTHY ,  Tahir GHANI ,  Sagar SUTHRAM

IPC: H01L29/423 ,  H01L27/12 ,  H01L27/092 ,  H01L23/528 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L27/1203 ,  H01L27/092 ,  H01L23/528 ,  H01L29/401 ,  H01L29/66439 ,  H01L29/66742

Abstract: Structures having AOI gates with routing across nanowires are described. In an example, an integrated circuit structure includes a stack of horizontal nanowires along a vertical direction. A gate stack is over the stack of horizontal nanowires and is surrounding a channel region of each of the horizontal nanowires, the gate stack having one or more cuts in the vertical direction.

公开(公告)号：US20230275157A1

公开(公告)日：2023-08-31

申请号：US18143549

申请日：2023-05-04

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand S. MURTHY ,  Tahir GHANI ,  Anupama BOWONDER

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7853 ,  H01L29/66818 ,  H01L29/165 ,  H01L29/7851

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20230197713A1

公开(公告)日：2023-06-22

申请号：US17554442

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Guillaume BOUCHE ,  Andy Chih-Hung WEI ,  Anand S. MURTHY ,  Aryan NAVABI-SHIRAZI ,  Mohammad HASAN

IPC: H01L27/088 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L27/088 ,  H01L21/823814 ,  H01L21/823412 ,  H01L27/092 ,  H01L21/823481 ,  H01L21/823418

Abstract: Gate-all-around integrated circuit structures having raised wall structures for epitaxial source or drain region confinement are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires. A gate stack is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and the second epitaxial source or drain structures. The intervening dielectric structure has a top surface above a top surface of the first and second vertical arrangements of nanowires. The intervening dielectric structure has a width at the top surface of the intervening dielectric structure less than a width below the top surface of the intervening dielectric structure.