公开(公告)号：US09811269B1

公开(公告)日：2017-11-07

申请号：US15395062

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Anand S. Ramalingam ,  Pranav Kalavade

IPC: G11C7/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0613 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2212/1016 ,  G06F2212/2022 ,  G06F2212/7204 ,  G06F2212/7205

Abstract: Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.

公开(公告)号：US09792997B2

公开(公告)日：2017-10-17

申请号：US15183582

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Neal R. Mielke ,  Krishna K. Parat ,  Shyam Sunder Raghunathan

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

公开(公告)号：US09703494B1

公开(公告)日：2017-07-11

申请号：US15276080

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade

IPC: G11C7/10 ,  G06F3/06 ,  G11C11/56 ,  G11C16/34 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5648

Abstract: In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to store a first page of data in a plurality of cells of the NAND flash memory in a first programming pass; and preserve the readability of the first page of data in the plurality of cells during a subsequent programming pass comprising a plurality of program loops, at least one of the plurality of program loops to comprise application of a first voltage to a first group of cells of the plurality of cells and application of a second voltage to a second group of cells of the plurality of cells, wherein the first group comprises cells that were not programmed in the first programming pass and the second group comprises cells that were programmed in the first programming pass.

公开(公告)号：US20170139626A1

公开(公告)日：2017-05-18

申请号：US15419563

申请日：2017-01-30

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Aliasgar Madraswala ,  Pranav Kalavade ,  Xin Guo ,  David Pelster ,  Myron Loewen ,  Feng Zhu ,  Brennan A. Watt

IPC: G06F3/06 ,  G06F12/0811

CPC classification number: G06F3/0625 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0688 ,  G06F12/0811 ,  G06F2212/283 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/225 ,  G11C2211/5641

Abstract: Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes setting an alternate data cache (PDC1) to a logical AND of a secondary data cache (SDC) and a primary data cache (PDC0). The PDC1 is set to a logical AND of the PDC1 and a first result of a first sense operation. The PDC0 is set to a logical AND of the PDC0 and an inverse value of the PDC1. The PDC1 is set to a logical AND of the SDC and the PDC0. The PDC1 is set to a logical AND of the PDC1 and an inverse value of a second result of a second sense operation. The SDC is set to a logical AND of the SDC and the PDC0. The SDC is set to a logical OR of the SDC or the PDC0. The PDC0 is set to a logical AND of the PDC0 and a third result of a third sensing operation.

公开(公告)号：US09570159B1

公开(公告)日：2017-02-14

申请号：US14884428

申请日：2015-10-15

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Aliasgar Madraswala ,  Pranav Kalavade ,  Xin Guo ,  David Pelster ,  Myron Loewen ,  Feng Zhu ,  Brennan A. Watt

IPC: G11C11/34 ,  G11C11/56 ,  G11C11/4096 ,  G11C16/22 ,  G11C7/10

CPC classification number: G06F3/0625 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0688 ,  G06F12/0811 ,  G06F2212/283 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/225 ,  G11C2211/5641

Abstract: Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes sending, upon detection of the power loss event, from a processor of the solid state drive, a command to abort an ongoing write operation of an aborted memory cell. In response to an indication that the ongoing write operation is aborted, the data to be written to the aborted memory cell is recovered. A first portion of the data to be written to the aborted memory cell is written to a first memory cell. A second portion of the data to be written to the aborted memory cell is written to a second memory cell.

Abstract translation: 公开了在功率损耗事件期间保存固态驱动器的数据的方法，装置，系统和制品。 一种示例性方法包括在从固态驱动器的处理器检测到功率损耗事件时发送中止正在进行的中止的存储器单元的写入操作的命令。 响应于正在进行的写入操作被中止的指示，将要被写入被中止的存储单元的数据被恢复。 要写入中止的存储单元的数据的第一部分被写入第一存储器单元。 要写入中止的存储单元的数据的第二部分被写入第二存储单元。

公开(公告)号：US09245645B2

公开(公告)日：2016-01-26

申请号：US13963629

申请日：2013-08-09

Applicant: INTEL CORPORATION

Inventor： Charan Srinivasan ,  Pranav Kalavade ,  Shyam Sunder Raghunathan ,  Krishna K. Parat

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5621

Abstract: Embodiments of the present disclosure include techniques and configurations for multi-pulse programming of a memory device. In one embodiment, a method includes applying multiple pulses to program one or more multi-level cells (MLCs) of a memory device, wherein individual pulses of the multiple pulses correspond with individual levels of the one or more MLCs and subsequent to applying the multiple pulses, verifying the programming of the individual levels of the one or more MLCs. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例包括用于存储器件的多脉冲编程的技术和配置。 在一个实施例中，一种方法包括应用多个脉冲来对存储器件的一个或多个多电平单元（MLC）进行编程，其中多个脉冲的各个脉冲与一个或多个MLC的各个级别对应，并且在施加多个 脉冲，验证一个或多个MLC的各个级别的编程。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20230154539A1

公开(公告)日：2023-05-18

申请号：US17528892

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Shantanu R. Rajwade ,  Christian Mion ,  Pranav Kalavade ,  Rohit S. Shenoy ,  Xin Sun ,  Kristopher Gaewsky

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G06F3/06

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3459 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/56

Abstract: In one embodiment, an apparatus comprises a memory comprising a group of memory cells coupled to a wordline; and a controller configured to skip programming of one or more pages of the group of memory cells responsive to a sequential write operation; and program the one or more pages of the group of memory cells responsive to one or more random write commands.

公开(公告)号：US11587874B2

公开(公告)日：2023-02-21

申请号：US16799448

申请日：2020-02-24

Applicant: Intel Corporation

Inventor： Sung-Taeg Kang ,  Pranav Kalavade ,  Owen W. Jungroth ,  Prasanna Srinivasan

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/528

Abstract: Apparatus, systems, or methods for a memory array having a plurality of word lines. A word line includes at least one word line plate, and the word line plate comprises a first material with a first resistivity. An edge of the word line plate is recessed and filled with a second material having a second resistivity that is lower than the first resistivity. As a result, the total resistance of the word line may be reduced compared to a word line using only the first material with the first resistivity. Other embodiments may also be described and claimed.

公开(公告)号：US20220101932A1

公开(公告)日：2022-03-31

申请号：US17032791

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Pranav Kalavade ,  Rohit S. Shenoy ,  Golnaz Karbasian

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

Abstract: A memory device comprising a memory array; and controller circuitry to apply a first pass voltage to a first plurality of unselected wordlines of the memory array during a string current sensing phase; and reduce the first pass voltage applied to the first plurality of unselected wordlines during a multistrobe sensing phase that follows the string current sensing phase.

公开(公告)号：US11270778B2

公开(公告)日：2022-03-08

申请号：US16852162

申请日：2020-04-17

Applicant: Intel Corporation

Inventor： Han Zhao ,  Pranav Kalavade ,  Krishna K. Parat

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/04

Abstract: Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.