公开(公告)号：US20200006631A1

公开(公告)日：2020-01-02

申请号：US16024411

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Tanay Gosavi ,  Justin Brockman ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Christopher Wiegand ,  Angeline Smith ,  Tofizur Rahman ,  Ian Young

IPC: H01L43/02 ,  G11C11/16 ,  H01L43/10 ,  H01L43/12

Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a magnetic tunnel junction (MTJ) device on a portion of the electrode. The electrode has a first SOC layer and a second SOC layer on a portion of the first SOC layer, where at least a portion of the first SOC layer at an interface with the second SOC layer includes oxygen.

公开(公告)号：US20200006626A1

公开(公告)日：2020-01-02

申请号：US16022094

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Angeline Smith ,  Ian Young ,  Kaan Oguz ,  Sasikanth Manipatruni ,  Christopher Wiegand ,  Kevin O'Brien ,  Tofizur Rahman ,  Noriyuki Sato ,  Benjamin Buford ,  Tanay Gosavi

IPC: H01L43/02 ,  H01L43/10 ,  H01L27/22

Abstract: An insertion layer for perpendicular spin orbit torque (SOT) memory devices between the SOT electrode and the free magnetic layer, memory devices and computing platforms employing such insertion layers, and methods for forming them are discussed. The insertion layer is predominantly tungsten and improves thermal stability and perpendicular magnetic anisotropy in the free magnetic layer.

公开(公告)号：US20200006424A1

公开(公告)日：2020-01-02

申请号：US16022564

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Angeline Smith ,  Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Tofizur Rahman ,  Gary Allen ,  Atm G. Sarwar ,  Ian Young ,  Hui Jae Yoo ,  Christopher Weigand ,  Benjamin Buford

IPC: H01L27/22 ,  G11C11/16 ,  H01F10/32 ,  H01L43/02 ,  H01L43/12 ,  H01F41/34

Abstract: A spin orbit torque (SOT) memory device includes a magnetic tunnel junction (MTJ) device with one end coupled with a first electrode and an opposite end coupled with a second electrode including a spin orbit torque material. In an embodiment, a second electrode is coupled with the free magnet and coupled between a pair of interconnect line segments. The second electrode and the pair of interconnect line segments include a spin orbit torque material. The second electrode has a conductive path cross-section that is smaller than a cross section of the conductive path in at least one of the interconnect line segments.

公开(公告)号：US20190386205A1

公开(公告)日：2019-12-19

申请号：US16012672

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Noriyuki Sato ,  Kevin O'Brien ,  Benjamin Buford ,  Christopher Wiegand ,  Angeline Smith ,  Tofizur Rahman ,  Ian Young

IPC: H01L43/04 ,  H01L43/10 ,  H01L43/08 ,  H01F10/32 ,  G11C11/16 ,  G11C11/18

Abstract: An apparatus is provided which comprises: a magnetic junction including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device; a second structure comprising one of a dielectric or metal; a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; a fourth structure comprising an antiferromagnetic (AFM) material, the fourth structure adjacent to the third structure; a fifth structure comprising a magnet with PMA, the fifth structure adjacent to the fourth structure; and an interconnect adjacent to the first structure, the interconnect comprising spin orbit material.

公开(公告)号：US20190386203A1

公开(公告)日：2019-12-19

申请号：US16012673

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-Ching Lin ,  Sasikanth Manipatruni ,  Ian Young

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01L27/22 ,  H01F10/32

Abstract: An apparatus is provided which comprises: a bit-line; a first word-line; a second word-line; and a source-line; a magnetic junction comprising a free magnet; an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the free magnet of the magnetic junction; and a first device (e.g., a selector device) coupled at one end of the interconnect and to the second word-line; and a second device coupled to the magnetic junction, the first word-line and the source-line.

公开(公告)号：US12125895B2

公开(公告)日：2024-10-22

申请号：US16915600

申请日：2020-06-29

Applicant: Intel Corporation

Inventor： Chelsey Dorow ,  Kevin O'Brien ,  Carl Naylor ,  Uygar Avci ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Tanay Gosavi ,  Shriram Shivaraman ,  Kirby Maxey

IPC: H01L29/66 ,  B82Y10/00 ,  B82Y25/00 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B63/00 ,  H10N70/20

CPC classification number: H01L29/66439 ,  H01L21/02568 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/78696 ,  H10B63/30 ,  H10B63/34 ,  H10N70/253

Abstract: A transistor includes a channel including a first layer including a first monocrystalline transition metal dichalcogenide (TMD) material, where the first layer is stoichiometric and includes a first transition metal. The channel further includes a second layer above the first layer, the second layer including a second monocrystalline TMD material, where the second monocrystalline TMD material includes a second transition metal and oxygen, and where the second layer is sub-stoichiometric. The transistor further includes a gate electrode above a first portion of the channel layer, a gate dielectric layer between the channel layer and the gate electrode, a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate electrode is between drain contact and the source contact.

公开(公告)号：US12113117B2

公开(公告)日：2024-10-08

申请号：US18130326

申请日：2023-04-03

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-ching Lin ,  Raseong Kim ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Ian Young

IPC: H01L29/51 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H03H9/17

CPC classification number: H01L29/516 ,  H01L27/0886 ,  H01L29/42356 ,  H01L29/78391 ,  H01L29/7851 ,  H03H9/17

Abstract: Describe is a resonator that uses ferroelectric (FE) materials in the gate of a transistor as a dielectric. The use of FE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, FE material expands or contacts depending on the applied electric field on the gate of the transistor. As such, acoustic waves are generated by switching polarization of the FE materials. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above the FE based transistor.

公开(公告)号：US11646374B2

公开(公告)日：2023-05-09

申请号：US16232615

申请日：2018-12-26

Applicant: Intel Corporation

Inventor： Ashish Verma Penumatcha ,  Tanay Gosavi ,  Uygar Avci ,  Ian A. Young

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  G11C11/22 ,  H01L29/417 ,  H01L21/28

CPC classification number: H01L29/78391 ,  G11C11/223 ,  G11C11/2275 ,  H01L29/40111 ,  H01L29/41725 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684

Abstract: Embodiments herein describe techniques for a semiconductor device including a gate stack with a ferroelectric-oxide layer above a channel layer and in contact with the channel layer, and a top electrode above the ferroelectric-oxide layer. The ferroelectric-oxide layer includes a domain wall between an area under a nucleation point of the top electrode and above a separation line of the channel layer between an ON state portion and an OFF state portion of the channel layer. A resistance between a source electrode and a drain electrode is modulated in a range between a first resistance value and a second resistance value, dependent on a position of the domain wall within the ferroelectric-oxide layer, a position of the ON state portion of the channel layer, and a position of the OFF state portion of the channel layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11646356B2

公开(公告)日：2023-05-09

申请号：US16238419

申请日：2019-01-02

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Chia-ching Lin ,  Raseong Kim ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Ian Young

IPC: H01L29/51 ,  H01L29/78 ,  H01L27/088 ,  H03H9/17 ,  H01L29/423

CPC classification number: H01L29/516 ,  H01L27/0886 ,  H01L29/42356 ,  H01L29/7851 ,  H01L29/78391 ,  H03H9/17

Abstract: Describe is a resonator that uses anti-ferroelectric (AFE) materials in the gate of a transistor as a dielectric. The use of AFE increases the strain/stress generated in the gate of the FinFET. Along with the usual capacitive drive, which is boosted with the increased polarization, additional current drive is also achieved from the piezoelectric response generated to due to AFE material. In some embodiments, the acoustic mode of the resonator is isolated using phononic gratings all around the resonator using the metal line above and vias' to body and dummy fins on the side. As such, a Bragg reflector is formed above or below the AFE based transistor. Increased drive signal from the AFE results in larger output signal and larger bandwidth.

公开(公告)号：US11621391B2

公开(公告)日：2023-04-04

申请号：US16236060

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Tanay Gosavi ,  Dmitri Nikonov ,  Kaan Oguz ,  Ian A. Young

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  H01F10/32 ,  G11C11/16 ,  G11C11/14 ,  H01L27/11

Abstract: A memory device comprises an interconnect comprises a spin orbit coupling (SOC) material. A free magnetic layer is on the interconnect, a barrier material is over the free magnetic layer and a fixed magnetic layer is over the barrier material, wherein the free magnetic layer comprises an antiferromagnet. In another embodiment, memory device comprises a spin orbit coupling (SOC) interconnect and an antiferromagnet (AFM) free magnetic layer is on the interconnect. A ferromagnetic magnetic tunnel junction (MTJ) device is on the AFM free magnetic layer, wherein the ferromagnetic MTJ comprises a free magnet layer, a fixed magnet layer, and a barrier material between the free magnet layer and the fixed magnet layer.