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公开(公告)号：US20180269220A1
公开(公告)日：2018-09-20
申请号：US15988828
申请日：2018-05-24
Applicant: International Business Machines Corporation
Inventor： Ramachandra Divakaruni , Arvind Kumar , Carl J. Radens
IPC: H01L27/11568 , H01L21/8234 , H01L29/66 , H01L27/12 , H01L21/28 , H01L29/792 , H01L29/40 , H01L27/088
CPC classification number: H01L27/11568 , H01L21/823431 , H01L27/0886 , H01L27/1203 , H01L29/40117 , H01L29/408 , H01L29/66833 , H01L29/792 , H01L29/7926
Abstract: A plurality of fin structures containing, from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of a first conductivity type, extend upwards from a surface of a first doped semiconductor portion of the first conductivity type. A trapping material (e.g., an electron-trapping material) is present along a bottom portion of sidewall surfaces of each non-doped semiconductor portion and on exposed portions of each first doped semiconductor portion. Functional gate structures straddle each fin structure. Metal lines are located above each fin structure and straddle each functional gate structure. Each metal line is orientated perpendicular to each functional gate structure and has a bottommost surface that is in direct physical contact with a portion of a topmost surface of each of the second doped semiconductor portions.
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42.发明授权公开(公告)号：US10026849B2
公开(公告)日：2018-07-17
申请号：US15259516
申请日：2016-09-08
Inventor： Lawrence A. Clevenger , Carl J. Radens , Yiheng Xu , John H. Zhang
IPC: H01L21/8234 , H01L27/146 , H01L29/786 , H01L29/66 , H01L29/24 , H01L29/49
Abstract: Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the metal gate and the contacts can be self-aligned to the sacrificial material.
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公开(公告)号：US10002876B2
公开(公告)日：2018-06-19
申请号：US14527256
申请日：2014-10-29
Applicant: International Business Machines Corporation
Inventor： Ramachandra Divakaruni , Arvind Kumar , Carl J. Radens
IPC: H01L21/8242 , H01L27/11568 , H01L27/088 , H01L21/8234 , H01L21/28 , H01L27/12 , H01L29/40 , H01L29/792 , H01L29/66
CPC classification number: H01L27/11568 , H01L21/823431 , H01L27/0886 , H01L27/1203 , H01L29/40117 , H01L29/408 , H01L29/66833 , H01L29/792 , H01L29/7926
Abstract: A plurality of fin structures containing, from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of a first conductivity type, extend upwards from a surface of a first doped semiconductor portion of the first conductivity type. A trapping material (e.g., an electron-trapping material) is present along a bottom portion of sidewall surfaces of each non-doped semiconductor portion and on exposed portions of each first doped semiconductor portion. Functional gate structures straddle each fin structure. Metal lines are located above each fin structure and straddle each functional gate structure. Each metal line is orientated perpendicular to each functional gate structure and has a bottommost surface that is in direct physical contact with a portion of a topmost surface of each of the second doped semiconductor portions.
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公开(公告)号：US20180061817A1
公开(公告)日：2018-03-01
申请号：US15802525
申请日：2017-11-03
Inventor： Lawrence A. Clevenger , Carl J. Radens , Yiheng Xu , John H. Zhang
IPC: H01L25/18 , H01L25/065 , H01L23/31 , H01L23/498 , H01L25/00 , H01L21/48 , H01L23/538
CPC classification number: H01L25/18 , H01L21/4846 , H01L23/13 , H01L23/15 , H01L23/3107 , H01L23/49827 , H01L23/49894 , H01L23/5389 , H01L25/0657 , H01L25/50 , H01L2224/32145 , H01L2224/32225 , H01L2225/06541 , H01L2225/06548 , H01L2225/06555 , H01L2225/06568 , H01L2225/06572 , H01L2225/06589 , H01L2225/06593 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1438 , H01L2924/15156 , H01L2924/15313 , H01L2924/157
Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the first stair, wherein the at least one additional chip is vertically spaced apart from the first chip.
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公开(公告)号：US09348680B2
公开(公告)日：2016-05-24
申请号：US14242418
申请日：2014-04-01
Applicant: International Business Machines Corporation
Inventor： Rajiv V. Joshi , Rouwaida N. Kanj , Sani R. Nassif , Carl J. Radens
CPC classification number: G06F11/076 , G06F11/008 , G06F11/079 , G06F17/5009 , G06F17/5022 , G06F2217/10
Abstract: A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.
Abstract translation: 提供了一种用于重用采样的机制，用于有效地进行细胞故障率估计过程变化和其他设计考虑。 首先，该机制对电路参数进行搜索，以确定相对于一组性能变量的故障。 对于单个故障区域，初始搜索可以是参数空间的均匀采样。 混合重要性抽样（MIS）有效地估计单个故障区域。 然后，该机制找到每个度量的重心，并发现重要性样本。 然后，对于对应于过程变化或其他设计考虑的每个新的原点，机制找到合适的投影并重新计算新的重要性抽样（IS）比率。
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Patent Agency Ranking
46.发明申请公开(公告)号：US20150279844A1
公开(公告)日：2015-10-01
申请号：US14736651
申请日：2015-06-11
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
IPC: H01L27/108 , H01L29/06 , H01L27/12
CPC classification number: H01L27/10823 , H01L21/76264 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/0653 , H01L29/66181
Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.
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公开(公告)号：US20150243510A1
公开(公告)日：2015-08-27
申请号：US14187598
申请日：2014-02-24
Inventor： Lawrence A. Clevenger , Carl J. Radens , Richard S. Wise , Edem Wornyo , Yiheng Xu , John Zhang
IPC: H01L21/308
CPC classification number: H01L29/0661 , H01L21/02071 , H01L21/0337 , H01L21/3085 , H01L21/3086 , H01L21/31138 , H01L21/31144 , H01L21/32139 , H01L29/66621 , H01L29/66795 , H01L51/0525
Abstract: An ashing chemistry employing a combination of Cl2 and N2 is provided, which removes residual material from sidewalls of a patterned metallic hard mask layer without residue such that the sidewalls of the patterned metallic hard mask layer are vertical. The vertical profiled of the sidewalls of the patterned metallic hard mask layer can be advantageously employed to reduce pattern factor dependency in the etch bias between the pattern transferred into an underlying layer and the pattern as formed on the metallic hard mask layer. Further, the ashing chemistry can be employed to enhance removal of stringers in vertical portions of a metallic material layer.
Abstract translation: 提供采用Cl 2和N 2的组合的灰化化学品，其从图案化的金属硬掩模层的侧壁除去剩余材料，而不残留物，使得图案化的金属硬掩模层的侧壁是垂直的。 图案化的金属硬掩模层的侧壁的垂直分布可以有利地用于减少转印到下层中的图案与形成在金属硬掩模层上的图案之间的蚀刻偏压中的图案因子依赖性。 此外，灰化化学可以用于增强在金属材料层的垂直部分中的桁条的去除。
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公开(公告)号：US09030295B2
公开(公告)日：2015-05-12
申请号：US13772651
申请日：2013-02-21
Applicant: International Business Machines Corporation
Inventor： Ira L. Allen , Lawrence A. Clevenger , Kevin S. Petrarca , Carl J. Radens
CPC classification number: G06Q30/0283 , G06Q10/08
Abstract: In a method for controlling pricing of a product, a radio frequency identification (RFID) tag having at least one processor is attached to a monitored product. A value indicative of a degree of exposure to an environmental condition is obtained. The obtained value is compared with a predetermined value range. A price of the monitored product is adjusted when the result of the comparison falls outside the predetermined value range.
Abstract translation: 在用于控制产品定价的方法中，具有至少一个处理器的射频识别（RFID）标签被附加到被监视的产品。 获得表示暴露于环境条件的程度的值。 将所获得的值与预定值范围进行比较。 当比较结果超出预定值范围时，调整被监视产品的价格。
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公开(公告)号：US08828521B2
公开(公告)日：2014-09-09
申请号：US13912593
申请日：2013-06-07
Applicant: International Business Machines Corporation
Inventor： Lawrence A. Clevenger , Timothy J. Dalton , Elbert E. Huang , Sampath Purushothaman , Carl J. Radens
IPC: B32B3/30 , H05K3/40 , H01L21/033 , H01B17/66 , H01L21/311 , H01L23/532
CPC classification number: H05K3/40 , H01B17/66 , H01L21/0337 , H01L21/31144 , H01L21/76822 , H01L23/53295 , H01L2924/0002 , Y10T156/1039 , Y10T156/1082 , Y10T428/24521 , Y10T428/24529 , Y10T428/24537 , Y10T428/24612 , Y10T428/24711 , H01L2924/00
Abstract: Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.
Abstract translation: 包含在互连叠层中具有纳米级波纹界面的界面的介电复合结构提供了增强的粘合强度和界面断裂韧性。 还描述了进一步包含波纹粘合促进剂层以进一步增加本征界面粘合性的复合结构。 还描述了使用自组装聚合物体系和图案转移方法形成纳米级波纹界面以实现这些结构的方法。
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公开(公告)号：US20130273325A1
公开(公告)日：2013-10-17
申请号：US13912593
申请日：2013-06-07
Applicant: International Business Machines Corporation
Inventor： Lawrence A. Clevenger , Timothy J. Dalton , Elbert E. Huang , Sampath Purushothaman , Carl J. Radens
IPC: H01B17/66
CPC classification number: H05K3/40 , H01B17/66 , H01L21/0337 , H01L21/31144 , H01L21/76822 , H01L23/53295 , H01L2924/0002 , Y10T156/1039 , Y10T156/1082 , Y10T428/24521 , Y10T428/24529 , Y10T428/24537 , Y10T428/24612 , Y10T428/24711 , H01L2924/00
Abstract: Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.
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