公开(公告)号：US09430396B2

公开(公告)日：2016-08-30

申请号：US14579934

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Rajesh Sankaran ,  Subramanya Dulloor ,  Sheng Li

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/128 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F3/0671 ,  G06F11/00 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0862 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/1027 ,  G06F2212/1032 ,  G06F2212/6028 ,  G06F2212/621

Abstract: A processor includes a processing core to execute an application including instructions encoding a transaction with a persistent memory via a volatile cache that includes a cache line associated with the transaction, the cache line being associated with a cache line status, and a cache controller operatively coupled to the volatile cache, the cache controller, in response to detecting a failure event, to, in response to determining that the cache line status that the cache line is committed, evict contents of the cache line to the persistent memory, and in response to determining that the cache line status indicating that the cache line is uncommitted, discard the contents of the cache line.

Abstract translation: 处理器包括处理核心，用于执行包括通过包括与事务相关联的高速缓存行的易失性高速缓冲存储器与持久存储器进行交易的指令的应用，所述高速缓存行与高速缓存行状态相关联，高速缓存控制器可操作地耦合 响应于确定高速缓存行被提交的高速缓存行状态，缓存控制器响应于检测到故障事件，将高速缓存行的内容驱逐到永久存储器，并且响应于缓存行 确定指示高速缓存行未被提交的高速缓存行状态，丢弃高速缓存行的内容。

公开(公告)号：US12164971B2

公开(公告)日：2024-12-10

申请号：US18301733

申请日：2023-04-17

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Rajesh Sankaran ,  Sanjay Kumar ,  Kun Tian ,  Philip Lantz

IPC: G06F9/50 ,  G06F15/76 ,  H04L51/226 ,  G06F15/17 ,  H04L61/59 ,  H04L67/2885

Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

公开(公告)号：US20240134803A1

公开(公告)日：2024-04-25

申请号：US18279029

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Phillip Lantz ,  Rajesh Sankaran ,  David Hansen ,  Evgeny V. Voevodin ,  Andrew Anderson ,  Lizhen You ,  Xin Zhou ,  Nikhil Talpallikar

IPC: G06F12/1009

CPC classification number: G06F12/1009

Abstract: An embodiment of an integrated circuit may comprise an array of hardware counters, and circuitry communicatively coupled to the array of hardware counters, the circuitry to count accesses to one or more selected pages of a memory with the array of hardware counters. Other embodiments are disclosed and claimed.

公开(公告)号：US11954062B2

公开(公告)日：2024-04-09

申请号：US17310540

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： Joydeep Ray ,  Niranjan Cooray ,  Subramaniam Maiyuran ,  Altug Koker ,  Prasoonkumar Surti ,  Varghese George ,  Valentin Andrei ,  Abhishek Appu ,  Guadalupe Garcia ,  Pattabhiraman K ,  Sungye Kim ,  Sanjay Kumar ,  Pratik Marolia ,  Elmoustapha Ould-Ahmed-Vall ,  Vasanth Ranganathan ,  William Sadler ,  Lakshminarayanan Striramassarma

IPC: G06F12/00 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

公开(公告)号：US20240054011A1

公开(公告)日：2024-02-15

申请号：US18233308

申请日：2023-08-12

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Philip R. Lantz ,  Narayan Ranganathan ,  Saurabh Gayen ,  Sanjay Kumar ,  Nikhil Rao ,  Dhananjay A. Joshi ,  Hai Ming Khor ,  Utkarsh Y. Kakaiya

IPC: G06F9/48 ,  G06F9/50 ,  G06F12/0802

CPC classification number: G06F9/4881 ,  G06F9/5027 ,  G06F12/0802

Abstract: Methods and apparatus relating to data streaming accelerators are described. In an embodiment, a hardware accelerator such as a Data Streaming Accelerator (DSA) logic circuitry performs data movement and/or data transformation for data to be transferred between a processor (having one or more processor cores) and a storage device. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230251986A1

公开(公告)日：2023-08-10

申请号：US18296875

申请日：2023-04-06

Applicant: Intel Corporation

Inventor： Philip R. Lantz ,  Sanjay Kumar ,  Rajesh M. Sankaran ,  Saurabh Gayen

IPC: G06F13/364 ,  G06F13/24 ,  G06F9/50

CPC classification number: G06F13/364 ,  G06F9/5027 ,  G06F13/24

Abstract: Embodiments of apparatuses, methods, and systems for highly scalable accelerators are described. In an embodiment, an apparatus includes an interface to receive a plurality of work requests from a plurality of clients and a plurality of engines to perform the plurality of work requests. The work requests are to be dispatched to the plurality of engines from a plurality of work queues. The work queues are to store a work descriptor per work request. Each work descriptor is to include all information needed to perform a corresponding work request.

公开(公告)号：US11656916B2

公开(公告)日：2023-05-23

申请号：US17361932

申请日：2021-06-29

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Rajesh Sankaran ,  Sanjay Kumar ,  Kun Tian ,  Philip Lantz

IPC: G06F9/50 ,  G06F15/76 ,  H04L51/226 ,  G06F15/17 ,  H04L67/2885 ,  H04L61/59

CPC classification number: G06F9/5077 ,  G06F9/5038 ,  G06F15/76 ,  H04L51/226 ,  G06F15/17 ,  H04L61/59 ,  H04L67/2885 ,  H04T2001/2093

Abstract: Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

公开(公告)号：US11269782B2

公开(公告)日：2022-03-08

申请号：US16772765

申请日：2018-03-28

Applicant: INTEL CORPORATION

Inventor： Kun Tian ,  Xiao Zheng ,  Ashok Raj ,  Sanjay Kumar ,  Rajesh Sankaran

IPC: G06F12/1036 ,  G06F9/455 ,  G06F12/1081

Abstract: Embodiment of this disclosure provides a mechanism to extend a workload instruction to include both untranslated and translated address space identifiers (ASIDs). In one embodiment, a processing device comprising a translation manager is provided. The translation manager receives a workload instruction from a guest application. The workload instruction comprises an untranslated (ASID) and a workload for an input/output (I/O) device. The untranslated ASID is translated to a translated ASID. The translated ASID inserted into a payload of the workload instruction. Thereupon, the payload is provided to a work queue of the I/O device to execute the workload based in part on at least one of: the translated ASID or the untranslated ASID.

公开(公告)号：US10817441B2

公开(公告)日：2020-10-27

申请号：US16370587

申请日：2019-03-29

Applicant: INTEL CORPORATION

Inventor： Sanjay Kumar ,  David Koufaty ,  Philip Lantz ,  Pratik Marolia ,  Rajesh Sankaran ,  Koen Koning

IPC: G06F13/16 ,  G06F12/1027 ,  G06F3/06

Abstract: The present disclosure is directed to systems and methods sharing memory circuitry between processor memory circuitry and accelerator memory circuitry in each of a plurality of peer-to-peer connected accelerator units. Each of the accelerator units includes virtual-to-physical address translation circuitry and migration circuitry. The virtual-to-physical address translation circuitry in each accelerator unit includes pages for each of at least some of the plurality of accelerator units. The migration circuitry causes the transfer of data between the processor memory circuitry and the accelerator memory circuitry in each of the plurality of accelerator circuits. The migration circuitry migrates and evicts data to/from accelerator memory circuitry based on statistical information associated with accesses to at least one of: processor memory circuitry or accelerator memory circuitry in one or more peer accelerator circuits. Thus, the processor memory circuitry and accelerator memory circuitry may be dynamically allocated to advantageously minimize system latency attributable to data access operations.

公开(公告)号：US10108556B2

公开(公告)日：2018-10-23

申请号：US15246811

申请日：2016-08-25

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Rajesh Sankaran ,  Subramanya Dulloor ,  Sheng Li

IPC: G06F12/12 ,  G06F12/128 ,  G06F12/0891 ,  G06F3/06 ,  G06F12/0808 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0895 ,  G06F11/00

Abstract: A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a near memory cache, wherein the near memory cache comprises a cache line comprising an identifier associated with the transaction and a status flag indicating whether the cache line is committed or uncommitted, and a cache controller operatively coupled to the near memory cache to determine, based on the status flag, what operation is to be performed with respect to contents of the cache line.