公开(公告)号：US11222895B2

公开(公告)日：2022-01-11

申请号：US16488231

申请日：2017-03-22

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek Sharma ,  Van Le

IPC: H01L27/108 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  H01L23/528 ,  H01L49/02 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786

Abstract: Memory devices in which a memory cell includes a thin film select transistor and a capacitor (1TFT-1C). A 2D array of metal-insulator-metal capacitors may be fabricated over an array of the TFTs. Adjacent memory cells coupled to a same bitline may employ a continuous stripe of thin film semiconductor material. An isolation transistor that is biased to remain off may provide electrical isolation between adjacent storage nodes of a bitline. Wordline resistance may be reduced with a wordline shunt fabricated in a metallization level and strapped to gate terminal traces of the TFTs at multiple points over a wordline length. The capacitor array may occupy a footprint over a substrate. The TFTs providing wordline and bitline access to the capacitors may reside substantially within the capacitor array footprint. Peripheral column and row circuitry may employ FETs fabricated over a substrate substantially within the capacitor array footprint.

公开(公告)号：US11171240B2

公开(公告)日：2021-11-09

申请号：US16646196

申请日：2017-10-12

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Yih Wang

IPC: H01L29/786 ,  H01L23/528 ,  H01L27/108 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49

Abstract: A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.

公开(公告)号：US10916583B2

公开(公告)日：2021-02-09

申请号：US16464023

申请日：2016-12-27

Applicant: INTEL CORPORATION

Inventor： Yih Wang

IPC: H01L27/22 ,  G11C5/06 ,  H01L27/24 ,  H01L43/04 ,  H01L43/06 ,  H01L43/08 ,  H01L43/10 ,  H01L43/14 ,  H01L45/00

Abstract: Circuits are described that use metallization on both sides techniques to integrate two different types of non-volatile embedded memory devices within a single monolithic integrated circuit device. In an embodiment, a monolithic integrated circuit structure is provided that includes a device layer having one or more logic transistors. A front side interconnect layer is provided above the device layer, as seen in a vertical cross-section taken through the monolithic integrated circuit from top to bottom. A back side interconnect layer is provided below the device layer, as seen in the vertical cross-section. A first type of non-volatile memory device is provided in the front side interconnect layer, and a second type of non-volatile memory device different from the first type of non-volatile memory device is provided in the back side interconnect layer. A back side contact may be used to connect the device layer to a back side interconnect layer.

公开(公告)号：US20200279953A1

公开(公告)日：2020-09-03

申请号：US16646196

申请日：2017-10-12

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Yih Wang

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/423 ,  H01L29/417 ,  H01L27/108 ,  H01L23/528

Abstract: A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.

公开(公告)号：US10672831B2

公开(公告)日：2020-06-02

申请号：US16594595

申请日：2019-10-07

Applicant: Intel Corporation

Inventor： Yih Wang ,  Patrick Morrow

IPC: H01L27/24 ,  H01L43/08 ,  H01L27/22 ,  H01L45/00 ,  H01L43/02 ,  G11C11/16 ,  G11C13/00

Abstract: A microelectronic memory having metallization layers formed on a back side of a substrate, wherein the metallization layers on back side may be used for the formation of source lines and word lines. Such a configuration may allow for a reduction in bit cell area, a higher memory array density, and lower source line and word line resistances. Furthermore, such a configuration may also provide the flexibility to independently optimize interconnect performance for logic and memory circuits.

公开(公告)号：US10416217B2

公开(公告)日：2019-09-17

申请号：US14749324

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Chia-Ching Lin ,  Yih Wang ,  Ian A. Young

IPC: G01R31/12 ,  G01R29/26 ,  G11C11/16 ,  G11C29/50 ,  G01R31/28

Abstract: Embodiments include a test circuit to test one or more magnetic tunnel junctions (MTJs) of a magnetic random access memory (MRAM). The test circuit may measure a 1/f noise of the MTJ in the time domain, and determine a power spectral density (PSD) of the 1/f noise. The test circuit may estimate one or more parameters of the MTJ and/or MRAM based on the PSD. For example, the test circuit may determine a noise parameter, such as a Hooge alpha parameter, based on the PSD, and may estimate the one or more parameters of the MTJ and/or MRAM based on the 1/f parameter. Other embodiments may be described and claimed.

公开(公告)号：US09997563B2

公开(公告)日：2018-06-12

申请号：US15596650

申请日：2017-05-16

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Tahir Ghani ,  Joseph M. Steigerwald ,  John H. Epple ,  Yih Wang

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

公开(公告)号：US09865322B2

公开(公告)日：2018-01-09

申请号：US15280935

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Cyrille Dray ,  Blake C. Lin ,  Fatih Hamzaoglu ,  Liqiong Wei ,  Yih Wang

IPC: G11C11/16 ,  G06F3/06

CPC classification number: G11C11/1675 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697

Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.

公开(公告)号：US09660181B2

公开(公告)日：2017-05-23

申请号：US13994715

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Tahir Ghani ,  Joseph M. Steigerwald ,  John H. Epple ,  Yih Wang

IPC: H01L43/12 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

公开(公告)号：US12191395B2

公开(公告)日：2025-01-07

申请号：US18494384

申请日：2023-10-25

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Shriram Shivaraman ,  Benjamin Chu-Kung ,  Yih Wang ,  Tahir Ghani

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/311 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H10B12/00

Abstract: Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.