公开(公告)号：US20180342614A1

公开(公告)日：2018-11-29

申请号：US15602884

申请日：2017-05-23

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H03K17/687 ,  H01L29/06

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

公开(公告)号：US10141230B2

公开(公告)日：2018-11-27

申请号：US15609563

申请日：2017-05-31

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/04 ,  H01L21/02 ,  H01L21/3065

Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate having a {100} crystallographic surface orientation, forming a second semiconductor layer on the substrate, patterning the first semiconductor layer and the second semiconductor layer into a first plurality of fins and a second plurality of fins, respectively, wherein the first and second plurality of fins extend vertically with respect to the substrate, covering the first plurality of fins and a portion of the substrate corresponding to the first plurality of fins, and epitaxially growing semiconductor layers on exposed portions of the second plurality of fins and on exposed portions of the substrate, wherein the epitaxially grown semiconductor layers on the exposed portions of the second plurality of fins increase a critical dimension of each of the second plurality of fins.

公开(公告)号：US10083962B2

公开(公告)日：2018-09-25

申请号：US15256284

申请日：2016-09-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  Sean Teehan

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08

CPC classification number: H01L27/0922 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.

公开(公告)号：US20180219101A1

公开(公告)日：2018-08-02

申请号：US15938367

申请日：2018-03-28

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L29/78618 ,  B82Y10/00 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H05K999/99

Abstract: A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.

公开(公告)号：US20180158818A1

公开(公告)日：2018-06-07

申请号：US15786828

申请日：2017-10-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/49

CPC classification number: H01L27/0886 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L2221/1063

Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

公开(公告)号：US20180083118A1

公开(公告)日：2018-03-22

申请号：US15355521

申请日：2016-11-18

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/311

CPC classification number: H01L29/6681 ,  H01L21/31111 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78696

Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.

公开(公告)号：US20180069003A1

公开(公告)日：2018-03-08

申请号：US15256284

申请日：2016-09-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  Sean Teehan

IPC: H01L27/092 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/08

CPC classification number: H01L27/0922 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.

公开(公告)号：US20170365525A1

公开(公告)日：2017-12-21

申请号：US15609563

申请日：2017-05-31

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/8238 ,  H01L29/16 ,  H01L27/092 ,  H01L29/04 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/161 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/3065 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161

Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate having a {100} crystallographic surface orientation, forming a second semiconductor layer on the substrate, patterning the first semiconductor layer and the second semiconductor layer into a first plurality of fins and a second plurality of fins, respectively, wherein the first and second plurality of fins extend vertically with respect to the substrate, covering the first plurality of fins and a portion of the substrate corresponding to the first plurality of fins, and epitaxially growing semiconductor layers on exposed portions of the second plurality of fins and on exposed portions of the substrate, wherein the epitaxially grown semiconductor layers on the exposed portions of the second plurality of fins increase a critical dimension of each of the second plurality of fins.

公开(公告)号：US20170330754A1

公开(公告)日：2017-11-16

申请号：US15627685

申请日：2017-06-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/033 ,  H01L29/66

CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/32105 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of a plurality of mandrels using an angled deposition process. A second sidewall of one or more of the plurality of mandrels is masked. Second spacers are formed on a second sidewall of all unmasked mandrels. The second sidewall of the one or more of the plurality of mandrels is unmasked. The mandrels are etched away. Fins are formed from a substrate using the first and second spacers as a mask.

公开(公告)号：US09786666B2

公开(公告)日：2017-10-10

申请号：US15158073

申请日：2016-05-18

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ryan O. Jung ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10 ,  H01L21/308 ,  H01L21/322

CPC classification number: H01L27/0924 ,  H01L21/3081 ,  H01L21/3221 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A silicon fin precursor is formed in an nFET device region and a fin stack comprising alternating material portions, and from bottom to top, of silicon and a silicon germanium alloy is formed in a pFET device region. A thermal anneal is then used to convert the fin stack into a silicon germanium alloy fin precursor. A thermal oxidation process follows that converts the silicon fin precursor into a silicon fin and the silicon germanium alloy fin precursor into a silicon germanium alloy fin. Functional gate structures can be formed straddling over each of the various fins.