公开(公告)号：US06638811B2

公开(公告)日：2003-10-28

申请号：US10157977

申请日：2002-05-31

申请人： Masayoshi Saito ,  Yoshitaka Nakamura ,  Hidekazu Goto ,  Keizo Kawakita ,  Satoru Yamada ,  Toshihiro Sekiguchi ,  Isamu Asano ,  Yoshitaka Tadaki ,  Takuya Fukuda ,  Masayuki Suzuki ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hideo Aoki ,  Masayoshi Hirasawa

发明人： Masayoshi Saito ,  Yoshitaka Nakamura ,  Hidekazu Goto ,  Keizo Kawakita ,  Satoru Yamada ,  Toshihiro Sekiguchi ,  Isamu Asano ,  Yoshitaka Tadaki ,  Takuya Fukuda ,  Masayuki Suzuki ,  Tsuyoshi Tamaru ,  Naoki Fukuda ,  Hideo Aoki ,  Masayoshi Hirasawa

IPC分类号： H01L218242

CPC分类号： H01L21/76855 ,  H01L21/28518 ,  H01L21/31604 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/40

摘要： In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

摘要翻译： 在具有电容器的位线结构的DRAM中，信息存储电容元件C的电容绝缘膜由诸如Ta 2 O 5（氧化钽）膜46的高电介质材料形成，位线BL和第一 - 与W膜形成的与外部电路至少底层的氧化硅膜28接触的层间布线23〜26，位线BL和布线23〜26配置在信息存储电容元件C的下方 从而在形成电容绝缘膜时进行的高温热处理方面提高了位线BL与布线23〜26之间界面处的粘附性和氧化硅膜。

公开(公告)号：US06548847B2

公开(公告)日：2003-04-15

申请号：US09899921

申请日：2001-07-09

申请人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

发明人： Jun Sugiura ,  Osamu Tsuchiya ,  Makoto Ogasawara ,  Fumio Ootsuka ,  Kazuyoshi Torii ,  Isamu Asano ,  Nobuo Owada ,  Mitsuaki Horiuchi ,  Tsuyoshi Tamaru ,  Hideo Aoki ,  Nobuhiro Otsuka ,  Seiichirou Shirai ,  Masakazu Sagawa ,  Yoshihiro Ikeda ,  Masatoshi Tsuneoka ,  Toru Kaga ,  Tomotsugu Shimmyo ,  Hidetsugu Ogishi ,  Osamu Kasahara ,  Hiromichi Enami ,  Atsushi Wakahara ,  Hiroyuki Akimori ,  Sinichi Suzuki ,  Keisuke Funatsu ,  Yoshinao Kawasaki ,  Tunehiko Tubone ,  Takayoshi Kogano ,  Ken Tsugane

IPC分类号： H01L2976

CPC分类号： H01L27/10852 ,  G03F7/70333 ,  G03F9/70 ,  H01L21/28512 ,  H01L21/76 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L23/291 ,  H01L23/4951 ,  H01L23/5258 ,  H01L23/532 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L27/0922 ,  H01L27/0928 ,  H01L27/10808 ,  H01L28/40 ,  H01L2223/54473 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  Y10S257/90 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

摘要翻译： 这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤 通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤， 面具已被删除。

公开(公告)号：US06528403B2

公开(公告)日：2003-03-04

申请号：US10013454

申请日：2001-12-13

申请人： Yoshikazu Tanabe ,  Isamu Asano ,  Makoto Yoshida ,  Naoki Yamamoto ,  Masayoshi Saito ,  Nobuyoshi Natsuaki

发明人： Yoshikazu Tanabe ,  Isamu Asano ,  Makoto Yoshida ,  Naoki Yamamoto ,  Masayoshi Saito ,  Nobuyoshi Natsuaki

IPC分类号： H01L214763

CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/32105 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/4941

摘要： With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.

公开(公告)号：US06417045B1

公开(公告)日：2002-07-09

申请号：US09642586

申请日：2000-08-22

申请人： Isamu Asano ,  Robert Tsu

发明人： Isamu Asano ,  Robert Tsu

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10897

摘要： In semiconductor integrated circuit device having a DRAM including a memory cell portion formed at a first portion of a main surface of a semiconductor substrate and a peripheral circuit portion formed at a second portion of the main surface of the semiconductor substrate, bit line conductors and first level interconnect conductors in the peripheral circuit portion for connecting the memory cell portion and the peripheral circuit portion so as to exchange signals between them are constituted by conductor layers that are formed simultaneously and hence, exist at the same level. The conductor layers exist at an outside position of the memory cell portion such as in the peripheral circuit portion, and the thickness of portions of the conductor layers constituting the first level interconnect conductors of the peripheral circuit portion is greater than the thickness of portions of the conductor layers constituting the bit line conductors. A position at which a transistor for selectively connecting the memory cell portion and the peripheral circuit portion is formed may be a boundary, or a position inside a boundary region between the memory cell portion and the peripheral circuit portion may be a boundary, where the thickness change is effected.

摘要翻译： 在具有形成在半导体衬底的主表面的第一部分处的存储单元部分和形成在半导体衬底的主表面的第二部分的外围电路部分的DRAM的半导体集成电路器件中，位线导体和第一 用于连接存储单元部分和外围电路部分以便在它们之间交换信号的外围电路部分中的高级互连导体由同时形成并因此存在于同一水平的导体层构成。 导体层存在于诸如周边电路部分的存储单元部分的外部位置，并且构成外围电路部分的第一级互连导体的导体层的部分的厚度大于外围电路部分的厚度 构成位线导体的导体层。 形成用于选择性地连接存储单元部分和外围电路部分的晶体管的位置可以是边界，或者存储单元部分和外围电路部分之间的边界区域内的位置可以是边界，其中厚度 改变了。

公开(公告)号：US06258649B1

公开(公告)日：2001-07-10

申请号：US09389231

申请日：1999-09-03

申请人： Yoshitaka Nakamura ,  Masayoshi Hirasawa ,  Isamu Asano ,  Tsuyoshi Tamaru ,  Satoru Yamada ,  Keizo Kawakita ,  Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Takuya Fukuda

发明人： Yoshitaka Nakamura ,  Masayoshi Hirasawa ,  Isamu Asano ,  Tsuyoshi Tamaru ,  Satoru Yamada ,  Keizo Kawakita ,  Toshihiro Sekiguchi ,  Yoshitaka Tadaki ,  Takuya Fukuda

IPC分类号： H01L218234

CPC分类号： H01L27/10894 ,  H01L21/28518 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76828 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/53223 ,  H01L27/10882 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.

摘要翻译： 为了提高连接到DRAM的每个信息存储电容元件的电极的馈电互连的连接可靠性，形成用于连接在每个存储单元选择MISFET上形成的信息存储电容元件的通孔和馈电互连 在与形成用于连接在信息存储电容元件上形成的外围电路中的第二布线层的互连的通孔和形成用于连接对应于第一布线层的互连的通孔中。

公开(公告)号：US4086815A

公开(公告)日：1978-05-02

申请号：US708251

申请日：1976-07-23

申请人： Isamu Asano ,  Mitsuru Tamai ,  Tadanori Yuhara ,  Takeshi Yasuhara

发明人： Isamu Asano ,  Mitsuru Tamai ,  Tadanori Yuhara ,  Takeshi Yasuhara

IPC分类号： G01L9/00 ,  G01L13/02 ,  G01L9/12

CPC分类号： G01L13/025 ,  G01L9/007 ,  G01L9/0072

摘要： A pressure sensing device is disclosed having the pressure sensing diaphragm positioned in a housing which is not stressed or enlarged by large static pressure. The housing is attached within a recess of a larger casing by means of a support diaphragm. The recesses are communicated with the interior of the housing by passages therethrough to equalize the pressure inside and outside the housing. The outer side of each casing forms a pressure reception chamber with a respective pressure receiving diaphragm. The latter chambers communicate with the recess via passages in the casing. The space between the pressure sensitive diaphragm and each pressure receiving diaphragm, including the housing interior chamber, the housing passage, the casing recess, the casing passage and the pressure receptive chamber, is filled with a fluid. The construction and filling is such that overpressure on one pressure receiving diaphram causes the entire housing to move toward the inner wall of the casing. However the latter diaphragm closes with the outer wall of the casing before the housing contacts the casing inner wall.

摘要翻译： 公开了一种压力感测装置，其具有位于壳体中的压力感测膜片，该壳体不受大的静压力的压力或增大。 壳体通过支撑膜片附接在较大壳体的凹部内。 凹槽通过其中的通道与壳体的内部连通，以均衡壳体内外的压力。 每个壳体的外侧形成具有相应的压力接收膜片的受压室。 后者室通过壳体中的通道与凹槽连通。 包括壳体内部室，壳体通道，壳体凹部，壳体通道和压力接收室之间的压力敏感隔膜和每个受压隔膜之间的空间填充有流体。 施工和填充使得在一个受压的压力下的超压使得整个壳体朝向壳体的内壁移动。 然而，在壳体接触壳体内壁之前，后一个隔膜与外壳的外壁相连。

公开(公告)号：US08637843B2

公开(公告)日：2014-01-28

申请号：US13370693

申请日：2012-02-10

申请人： Isamu Asano

发明人： Isamu Asano

IPC分类号： H01L29/02

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/144

摘要： Disclosed herein is a device that includes: an interlayer insulation film having a through hole; and a phase change storage element provided in the through hole. The phase change storage element includes: an outer electrode being a conductive film of cylindrical shape and being formed along an inner wall of the through hole; a buffer insulation film being an insulation film of cylindrical shape and being formed along an inner wall of the outer electrode, an upper end of the buffer insulation film being recessed in part to form a recess; a phase change film filling an interior of the recess; and an inner electrode being a conductive film formed along an inner wall of the buffer insulation film including a surface of the phase change film.

摘要翻译： 本文公开了一种装置，其包括：具有通孔的层间绝缘膜; 以及设置在通孔中的相变存储元件。 相变存储元件包括：外电极，其是圆柱形导电膜，沿着通孔的内壁形成; 缓冲绝缘膜是圆柱形绝缘膜，沿着外电极的内壁形成，缓冲绝缘膜的上端部分地凹入以形成凹部; 填充所述凹部内部的相变膜; 并且内部电极是沿着包括相变膜的表面的缓冲绝缘膜的内壁形成的导电膜。

公开(公告)号：US20100284218A1

公开(公告)日：2010-11-11

申请号：US12772340

申请日：2010-05-03

申请人： Kazuo AIZAWA ,  Isamu Asano ,  Junji Tominaga ,  Alexander Kolobov ,  Paul Fons ,  Robert Simpson

发明人： Kazuo AIZAWA ,  Isamu Asano ,  Junji Tominaga ,  Alexander Kolobov ,  Paul Fons ,  Robert Simpson

IPC分类号： G11C11/34 ,  H01L29/66 ,  H01L21/06 ,  G11C29/00

CPC分类号： G11C13/0004 ,  G11C2213/55 ,  G11C2213/72 ,  G11C2213/79 ,  H01L45/065 ,  H01L45/144 ,  H01L45/1625

摘要： To include a superlattice laminate having laminated thereon a first crystal layer of which crystal lattice is a cubic crystal and in which positions of constituent atoms are reversibly replaced by application of energy, and a second crystal layer having a composition different from that of the first crystal layer, and an orientation layer that is an underlaying layer of the superlattice laminate and causes a laminated surface of the first crystal layer to be (111)-orientated. According to the present invention, the laminated surface of the first crystal layer can be (111)-orientated by using the orientation layer as an underlaying layer. In the first crystal layer of which laminated surface is (111)-orientated, a crystal structure reversibly changes when a relatively low energy is applied. Therefore, characteristics of a superlattice device having this crystal layer can be enhanced.

摘要翻译： 为了包括其上层压有晶格为立方晶的第一晶体层，其中构成原子的位置被能量可逆地替代的超晶格层压体，以及具有与第一晶体不同的组成的第二晶体层 层，以及作为超晶格层叠体的垫层的取向层，使第一结晶层的层叠表面（111）取向。 根据本发明，通过使用取向层作为底层，第一晶体层的层叠表面可以是（111）取向的。 在层叠表面为（111）取向的第一晶体层中，当施加相对低的能量时，晶体结构可逆地变化。 因此，可以提高具有该晶体层的超晶格器件的特性。

公开(公告)号：US07671356B2

公开(公告)日：2010-03-02

申请号：US11265275

申请日：2005-11-03

申请人： Isamu Asano ,  Tyler A. Lowrey

发明人： Isamu Asano ,  Tyler A. Lowrey

IPC分类号： H01L47/00

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  G11C2213/52 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

摘要： A non-volatile memory element comprising a bottom electrode 12, a top electrode 17 provided on the bottom electrode 12, and a recording layer 18 containing phase change material connected between the bottom electrode 12 and the top electrode 17. In accordance with this invention, the top electrode 17 is in contact with a growth initiation surface 18a of the recording layer 17. This structure can be obtained by forming the top electrode 17 before the recording layer 18, resulting in a three-dimensional structure. This decreases heat dissipation to the bit line without increasing the thickness of the recording layer 18.

摘要翻译： 包括底部电极12，设置在底部电极12上的顶部电极17和包含连接在底部电极12和顶部电极17之间的相变材料的记录层18的非易失性存储元件。根据本发明， 顶部电极17与记录层17的生长起始表面18a接触。这种结构可以通过在记录层18之前形成顶部电极17而获得，从而形成三维结构。 这降低了对位线的散热，而不增加记录层18的厚度。

公开(公告)号：US07554147B2

公开(公告)日：2009-06-30

申请号：US11374074

申请日：2006-03-14

申请人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

发明人： Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai ,  Yukio Fuji ,  Kazuhiko Kajigaya

IPC分类号： H01L27/108

CPC分类号： G11C13/0004 ,  G11C11/005 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

摘要： A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.

摘要翻译： 其中安装了DRAM和相变存储器（PCRAM）的存储器件具有形成在与DRAM位线共享的导电层上的DRAM位线，PCRAM位线或PCRAM源线，以及读出放大器 连接在DRAM位线和PCRAM位线之间。 存储器件还具有设置在DRAM位线的上层上的电容元件和设置在PCRAM位线的上层上的相变元件。 电容元件的下电极和相变存储元件的下电极形成在共用导电层上。