公开(公告)号：US08704280B2

公开(公告)日：2014-04-22

申请号：US13240782

申请日：2011-09-22

Applicant: Jeff J. Xu

Inventor： Jeff J. Xu

IPC: H01L29/66

CPC classification number: H01L29/4966 ,  H01L29/165 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7845 ,  H01L29/7848

Abstract: A semiconductor device with a metal gate is disclosed. The device includes a semiconductor substrate including a plurality of source and drain features to form a p-channel and an n-channel. The device also includes a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a high-k (HK) dielectric layer formed over the semiconductor substrate. A tensile stress HK capping layer is formed on top of the HK dielectric layer in close proximity to the p-channel, and a compressive stress HK N-work function (N-WF) metal layer is formed on top of the HK dielectric layer in close proximity to the n-channel. A stack of metal gate layers is deposited over the capping layers.

Abstract translation: 公开了一种具有金属栅极的半导体器件。 该器件包括具有多个源极和漏极特征以形成p沟道和n沟道的半导体衬底。 该器件还包括位于半导体衬底上的栅堆叠并且设置在源极和漏极特征之间。 栅堆叠包括形成在半导体衬底上的高k（HK）电介质层。 在紧邻p沟道的HK电介质层的顶部上形成拉伸应力HK覆盖层，并且在HK介电层的顶部形成压缩应力HKN-功函数（N-WF）金属层 靠近n通道。 一叠金属栅极层沉积在覆盖层上。

公开(公告)号：US08497528B2

公开(公告)日：2013-07-30

申请号：US12775006

申请日：2010-05-06

Applicant: Tsung-Lin Lee ,  Chih-Hao Chang ,  Chih-Hsin Ko ,  Feng Yuan ,  Jeff J. Xu

Inventor： Tsung-Lin Lee ,  Chih-Hao Chang ,  Chih-Hsin Ko ,  Feng Yuan ,  Jeff J. Xu

IPC: H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.

Abstract translation: 一种用于衬底上的场效应晶体管的结构，其包括栅极堆叠，隔离结构以及位于栅叠层和隔离结构之间的衬底顶表面下方的源极/漏极（S / D）凹槽。 该凹腔具有下部和上部。 下部具有第一应变层和第一介电膜。 第一应变层设置在隔离结构和第一介电膜之间。 第一电介质膜的厚度小于第一应变层的厚度。 上部具有覆盖在第一应变层和第一介电膜上的第二应变层。

公开(公告)号：US20130078779A1

公开(公告)日：2013-03-28

申请号：US13244358

申请日：2011-09-24

Applicant: Jeff J. Xu

Inventor： Jeff J. Xu

IPC: H01L21/336 ,  H01L21/20

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: A semiconductor device with a metal gate is disclosed. The device includes a semiconductor substrate, source and drain features on the semiconductor substrate, and a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes an interfacial layer (IL) layer, a high-k (HK) dielectric layer formed over the semiconductor substrate, an oxygen scavenging metal formed on top of the HK dielectric layer, a scaling equivalent oxide thickness (EOT) formed by using a low temperature oxygen scavenging technique, and a stack of metals gate layers deposited over the oxygen scavenging metal layer.

Abstract translation: 公开了一种具有金属栅极的半导体器件。 该器件包括半导体衬底，半导体衬底上的源极和漏极特征，以及位于半导体衬底上并设置在源极和漏极特征之间的栅极堆叠。 栅极堆叠包括界面层（IL）层，形成在半导体衬底上的高k（HK）电介质层，形成在HK电介质层顶部的氧清除金属，由 使用低温氧气清除技术，以及沉积在氧清除金属层上的金属栅层的堆叠。

公开(公告)号：US20130075826A1

公开(公告)日：2013-03-28

申请号：US13240782

申请日：2011-09-22

Applicant: Jeff J. Xu

Inventor： Jeff J. Xu

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L29/165 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7845 ,  H01L29/7848

Abstract: A semiconductor device with a metal gate is disclosed. The device includes a semiconductor substrate including a plurality of source and drain features to form a p-channel and an n-channel. The device also includes a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a high-k (HK) dielectric layer formed over the semiconductor substrate. A tensile stress HK capping layer is formed on top of the HK dielectric layer in close proximity to the p-channel, and a compressive stress HK N-work function (N-WF) metal layer is formed on top of the HK dielectric layer in close proximity to the n-channel. A stack of metal gate layers is deposited over the capping layers.

Abstract translation: 公开了一种具有金属栅极的半导体器件。 该器件包括具有多个源极和漏极特征以形成p沟道和n沟道的半导体衬底。 该器件还包括位于半导体衬底上的栅堆叠并且设置在源极和漏极特征之间。 栅堆叠包括形成在半导体衬底上的高k（HK）电介质层。 在紧邻p沟道的HK电介质层的顶部上形成拉伸应力HK覆盖层，并且在HK介电层的顶部形成压缩应力HKN-功函数（N-WF）金属层 靠近n通道。 一叠金属栅极层沉积在覆盖层上。

公开(公告)号：US20120091528A1

公开(公告)日：2012-04-19

申请号：US12906820

申请日：2010-10-18

Applicant: Chih-Hao Chang ,  Jeff J. Xu

Inventor： Chih-Hao Chang ,  Jeff J. Xu

IPC: H01L27/12 ,  H01L21/336

CPC classification number: H01L27/0886 ,  H01L27/12 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a fin structure over the semiconductor substrate, the fin structure including a first material portion over the semiconductor substrate and a second material portion over the first material portion; forming a gate structure over a portion of the fin structure, such that the gate structure traverses the fin structure, thereby separating a source region and a drain region of the fin structure, wherein the source and drain regions of the fin structure define a channel therebetween; removing the second material portion from the source and drain regions of the fin structure; and after removing the second material portion, forming a third material portion in the source and drain regions of the fin structure.

Abstract translation: 公开了一种用于制造FinFET器件的FinFET器件和方法。 一种示例性方法包括提供半导体衬底; 在所述半导体衬底上形成翅片结构，所述翅片结构包括所述半导体衬底上的第一材料部分和所述第一材料部分上的第二材料部分; 在翅片结构的一部分上形成栅极结构，使得栅极结构穿过翅片结构，从而分离翅片结构的源极区域和漏极区域，其中鳍状结构的源极和漏极区域在其间限定通道 ; 从翅片结构的源区和漏区移除第二材料部分; 并且在去除第二材料部分之后，在鳍结构的源极和漏极区域中形成第三材料部分。

公开(公告)号：US20120021589A1

公开(公告)日：2012-01-26

申请号：US13248932

申请日：2011-09-29

Applicant: Ming-Feng Shieh ,  Shinn-Sheng Yu ,  Anthony Yen ,  Shao-Ming Yu ,  Chang-Yun Chang ,  Jeff J. Xu ,  Clement Hsingjen Wann

Inventor： Ming-Feng Shieh ,  Shinn-Sheng Yu ,  Anthony Yen ,  Shao-Ming Yu ,  Chang-Yun Chang ,  Jeff J. Xu ,  Clement Hsingjen Wann

IPC: H01L21/311 ,  H01L21/30

CPC classification number: H01L27/0203 ,  G03F1/00 ,  G03F1/36 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/66795

Abstract: Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.

Abstract translation: 提供了一种包括光掩模的光刻设备。 光掩模包括具有多个特征的图案，在示例中为虚线特征。 该图案包括呈局部网格阵列形式的第一区域和其中至少一个特征具有增加的宽度的第二区域。 该装置可以包括可以限定有源区域的第二光掩模。 具有增加的宽度的特征可以与所定义的有效区域相邻并且在外部。

公开(公告)号：US07989355B2

公开(公告)日：2011-08-02

申请号：US12370152

申请日：2009-02-12

Applicant: Ming-Feng Shieh ,  Shinn-Sheng Yu ,  Anthony Yen ,  Ming-Ching Chang ,  Jeff J. Xu

Inventor： Ming-Feng Shieh ,  Shinn-Sheng Yu ,  Anthony Yen ,  Ming-Ching Chang ,  Jeff J. Xu

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/3086 ,  H01L21/3088 ,  H01L21/823828 ,  H01L21/823871 ,  Y10S438/947

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a mask layer over a substrate, forming a dummy layer having a first dummy feature and a second dummy feature over the mask layer, forming first and second spacer roofs to cover a top portion of the first and second dummy features, respectively, and forming first and second spacer sleeves to encircle side portions of the first and second dummy features, respectively, removing the first spacer roof and the first dummy feature while protecting the second dummy feature, removing a first end portion and a second end portion of the first spacer sleeve to form spacer fins, and patterning the mask layer using the spacer fins as a first mask element and the second dummy feature as a second mask element.

Abstract translation: 本公开提供了一种制造半导体器件的方法，该半导体器件包括在衬底上形成掩模层，在掩模层上形成具有第一虚拟特征和第二虚拟特征的虚设层，形成第一和第二间隔物顶部以覆盖顶部 分别形成第一和第二间隔套筒以分别围绕第一和第二虚拟特征的侧面部分，去除第一间隔物顶部和第一虚拟特征，同时保护第二虚拟特征，去除 第一间隔套筒的第一端部和第二端部，以形成间隔件翅片，并且使用间隔件翅片作为第一掩模元件并将第二虚拟特征图案化为掩模层作为第二掩模元件。

公开(公告)号：US20110169104A1

公开(公告)日：2011-07-14

申请号：US12687574

申请日：2010-01-14

Applicant: Jeff J. Xu ,  Liang-Gi Yao ,  Ta-Ming Kuan

Inventor： Jeff J. Xu ,  Liang-Gi Yao ,  Ta-Ming Kuan

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L21/2822 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides methods and apparatus of fluorine passivation in IC device fabrication. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate and passivating a surface of the substrate with a mixture of hydrofluoric acid and alcohol to form a fluorine-passivated surface. The method further includes forming a gate dielectric layer over the fluorine-passivated surface, and then forming a metal gate electrode over the gate dielectric layer. A semiconductor device fabricated by such a method is also disclosed.

Abstract translation: 本公开提供了IC器件制造中氟钝化的方法和装置。 在一个实施例中，制造半导体器件的方法包括提供衬底并用氢氟酸和醇的混合物钝化衬底的表面以形成氟钝化表面。 该方法还包括在氟钝化表面上形成栅极电介质层，然后在栅极介电层上形成金属栅电极。 还公开了通过这种方法制造的半导体器件。

公开(公告)号：US20110169085A1

公开(公告)日：2011-07-14

申请号：US13041066

申请日：2011-03-04

Applicant: Jeff J. Xu ,  Clement H. Wann ,  Chi Chieh Yeh ,  Chi-Sheng Chang

Inventor： Jeff J. Xu ,  Clement H. Wann ,  Chi Chieh Yeh ,  Chi-Sheng Chang

IPC: H01L27/092

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A CMOS FinFET semiconductor device provides an NMOS FinFET device that includes a compressive stress metal gate layer over semiconductor fins and a PMOS FinFET device that includes a tensile stress metal gate layer over semiconductor fins. A process for forming the same includes a selective annealing process that selectively converts a compressive metal gate film formed over the PMOS device to the tensile stress metal gate film.

Abstract translation: CMOS FinFET半导体器件提供了一种NMOS FinFET器件，其包括半导体鳍片上的压应力金属栅极层和包括半导体鳍片上的拉应力金属栅极层的PMOS FinFET器件。 其形成方法包括选择性退火工艺，其选择性地将形成在PMOS器件上的压电金属栅极膜转换为拉伸应力金属栅极膜。

公开(公告)号：US20100264468A1

公开(公告)日：2010-10-21

申请号：US12425854

申请日：2009-04-17

Applicant: Jeff J. Xu

Inventor： Jeff J. Xu

IPC: H01L29/78 ,  H01L21/20

CPC classification number: H01L29/66795

Abstract: The present disclosure provides a FinFET element and method of fabricating a FinFET element. The FinFET element includes a germanium-FinFET element (e.g., a multi-gate device including a Ge-fin). In one embodiment, the method of fabrication the Ge-FinFET element includes forming silicon fins on a substrate and selectively growing an epitaxial layer including germanium on the silicon fins. A Ge-condensation process may then be used to selectively oxidize the silicon of the Si-fin and transform the Si-fin to a Ge-fin. The method of fabrication provided may allow use of SOI substrate or bulk silicon substrates, and CMOS-compatible processes to form the Ge-FinFET element.

Abstract translation: 本公开提供了FinFET元件和制造FinFET元件的方法。 FinFET元件包括锗-FnFET元件（例如，包括Ge鳍的多栅极器件）。 在一个实施例中，制造Ge-FinFET元件的方法包括在衬底上形成硅散热片，并在硅片上选择性地生长包括锗的外延层。 然后可以使用Ge缩合过程来选择性地氧化Si鳍的硅并将Si鳍转化为Ge鳍。 提供的制造方法可以允许使用SOI衬底或体硅衬底以及CMOS兼容工艺来形成Ge-FinFET元件。