公开(公告)号：US07601607B2

公开(公告)日：2009-10-13

申请号：US11434318

申请日：2006-05-15

申请人： Wuping Liu ,  Raymond Joy ,  Beichao Zhang ,  Liang Choo Hsia ,  Boon Meng Seah ,  Shyam Pal

发明人： Wuping Liu ,  Raymond Joy ,  Beichao Zhang ,  Liang Choo Hsia ,  Boon Meng Seah ,  Shyam Pal

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/02063 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76814

摘要： An embodiment of the invention shows a process to form a damascene opening preferably without hardmask overhang or dielectric layer undercut/void. The low-k dielectric material can be sandwiched in two hardmask films to form the dielectric film through which an interconnect opening is etched. A first example embodiment comprises the following. We form a lower interconnect and an insulating layer over a semiconductor structure. We form a first hardmask a dielectric layer, and a second hardmask layer, over the lower interconnect and insulating layer. We etch a first interconnect opening in the first hardmask, the dielectric layer and the second hardmask layer. Lastly, we form an interconnect in the first interconnect opening.

摘要翻译： 本发明的一个实施例示出了一种形成镶嵌开口的方法，优选地不具有硬掩模悬垂或电介质层底切/空隙。 低k电介质材料可以被夹在两个硬掩模膜中以形成蚀刻互连开口的电介质膜。 第一示例性实施例包括以下。 我们在半导体结构上形成下互连和绝缘层。 我们在下互连和绝缘层上形成第一硬掩模介电层和第二硬掩模层。 我们蚀刻第一硬掩模，电介质层和第二硬掩模层中的第一互连开口。 最后，我们在第一个互连开口中形成互连。

公开(公告)号：US07528445B2

公开(公告)日：2009-05-05

申请号：US11380378

申请日：2006-04-26

申请人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

发明人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

IPC分类号： H01L29/76 ,  H01L31/113 ,  H01L21/338

CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.

摘要翻译： 提供一种用于形成半导体器件的系统。 在半导体衬底上形成栅介电材料层，栅极材料层和盖材料层。 盖材料和栅极材料的一部分被加工以形成盖和门体部分。 门体部分上的翼部由栅极材料的剩余部分形成。 栅极主体部分的翼部的下方的栅介质材料被去除以形成栅极电介质。 使用门主体部分和机翼，在半导体衬底中形成轻掺杂的源极/漏极区域。

公开(公告)号：US07524755B2

公开(公告)日：2009-04-28

申请号：US11358934

申请日：2006-02-22

申请人： Johnny Widodo ,  Bei Chao Zhang ,  Tong Qing Chen ,  Yong Kong Siew ,  Fan Zhang ,  San Leong Liew ,  John Sudijono ,  Liang Choo Hsia

发明人： Johnny Widodo ,  Bei Chao Zhang ,  Tong Qing Chen ,  Yong Kong Siew ,  Fan Zhang ,  San Leong Liew ,  John Sudijono ,  Liang Choo Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05073 ,  H01L2224/05546 ,  H01L2224/05647 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/01039 ,  H01L2924/00

摘要： A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.

摘要翻译： 形成用于互连的CuSiN构成的阻挡层和盖的方法。 我们在半导体结构上的电介质层中提供互连开口。 通过与第一铜层反应，在互连开口的侧壁和底部上形成CuSiN阻挡层。 然后，我们在填充互连开口的CuSiN层上形成互连。 我们可以在互连的顶部表面上形成CuSiN覆盖层。

公开(公告)号：US20070293039A1

公开(公告)日：2007-12-20

申请号：US11454397

申请日：2006-06-16

申请人： Xiaomei Bu ,  Alex See ,  Fan Zhang ,  Jane Hui ,  Tae Jong Lee ,  Liang Choo Hsia

发明人： Xiaomei Bu ,  Alex See ,  Fan Zhang ,  Jane Hui ,  Tae Jong Lee ,  Liang Choo Hsia

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/288 ,  H01L21/2885 ,  H01L21/76873 ,  H01L21/76877

摘要： A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.

摘要翻译： 公开了一种在电介质层中填充间隙的方法。 提供具有包含要填充铜的间隙的电介质层的晶片，其中一些间隙表示为更深的间隙，其纵横比大到使用ECP填充这些间隙的铜可导致针孔状空隙。 形成覆盖的共形金属阻挡层，然后将晶片浸没在无电镀平板上的覆盖层保形铜种子层的溶液中。 用铜部分填充更深的间隙可以减少较深间隙的有效纵横比，使得ECP可以用于完成间隙的铜填充而不形成针孔如空隙的程度。 然后使用ECP来完成间隙的铜填充。 对晶片进行退火并进行CMP以平坦化表面，产生其中间隙被铜填充并由介电层分离的结构。

公开(公告)号：US07202164B2

公开(公告)日：2007-04-10

申请号：US10992894

申请日：2004-11-19

申请人： Jinping Liu ,  Hwa Weng Koh ,  Dong Kyun Sohn ,  Liang Choo Hsia

发明人： Jinping Liu ,  Hwa Weng Koh ,  Dong Kyun Sohn ,  Liang Choo Hsia

IPC分类号： H01L21/8238

CPC分类号： H01L21/0214 ,  H01L21/02238 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518

摘要： A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics are to be disposed. An oxide is formed over the surfaces. A silicon layer is formed over the oxide layer. A nitridation process is performed. An optional high temperature annealing step may be performed.

摘要翻译： 公开了一种形成栅介质层的方法。 该方法包括以下步骤。 提供了具有硅区域的衬底，所述硅区域包含要在其上设置栅极电介质的表面。 在表面上形成氧化物。 在氧化物层上形成硅层。 进行氮化处理。 可以进行可选的高温退火步骤。

公开(公告)号：US20060180848A1

公开(公告)日：2006-08-17

申请号：US11380378

申请日：2006-04-26

申请人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

发明人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.

摘要翻译： 提供一种用于形成半导体器件的系统。 在半导体衬底上形成栅介电材料层，栅极材料层和盖材料层。 盖材料和栅极材料的一部分被加工以形成盖和门体部分。 门体部分上的翼部由栅极材料的剩余部分形成。 栅极主体部分的翼部的下方的栅介质材料被去除以形成栅极电介质。 使用门主体部分和机翼，在半导体衬底中形成轻掺杂的源极/漏极区域。

公开(公告)号：US06586314B1

公开(公告)日：2003-07-01

申请号：US10266952

申请日：2002-10-08

申请人： Soh Yun Siah ,  Liang Choo Hsia ,  Jia Zhen Zheng ,  Chew Hoe Ang

发明人： Soh Yun Siah ,  Liang Choo Hsia ,  Jia Zhen Zheng ,  Chew Hoe Ang

IPC分类号： H01L2176

CPC分类号： H01L21/76235

摘要： A method of forming a shallow trench isolation (STI), region in a semiconductor substrate featuring a process sequence that results in desired rounded corners for the sides of active device regions located butting the STI region, has been developed. The process sequence features formation of, followed by removal of, a silicon dioxide layer which was thermally grown in a top portion of the semiconductor substrate, wherein the top portion of semiconductor was subjected to an ion implantation procedure prior to the oxidation procedure. The above process sequence results in a recessed portion of semiconductor located adjacent to unoxidized portions of semiconductor which underlay an oxidation resistant shape, and feature rounded corners. Insulator spacers are then formed on the sides of the oxidation resistant shape, overlying and protecting the rounded comers of subsequent active device regions from a dry etch procedure used to selectively define a shallow trench shape in the exposed semiconductor region. Insulator filling and planarization procedures result in the formation of an STI region, located adjacent to active device regions which feature the desired rounded corners.

摘要翻译： 已经开发了在半导体衬底中形成浅沟槽隔离（STI）区域的方法，该半导体衬底的特征在于产生针对STI区域的有源器件区域的侧面的期望的圆角的工艺序列。 处理顺序特征在于形成，随后除去在半导体衬底的顶部热生长的二氧化硅层，其中半导体的顶部在氧化过程之前进行离子注入工艺。 上述处理顺序导致位于半导体的未氧化部分附近的半导体的凹陷部分，其具有抗氧化的形状，并且具有圆角。 然后在耐氧化形状的侧面上形成绝缘体间隔物，覆盖并保护随后的有源器件区域的圆角从用于在暴露的半导体区域中选择性地限定浅沟槽形状的干蚀刻工艺。 绝缘体填充和平坦化程序导致STI区域的形成，其位于具有所需圆角的有源器件区域附近。

公开(公告)号：US5827780A

公开(公告)日：1998-10-27

申请号：US626111

申请日：1996-04-01

申请人： Liang Choo Hsia ,  Thomas Tong Long Chang

发明人： Liang Choo Hsia ,  Thomas Tong Long Chang

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H01L21/465 ,  G03C5/00

CPC分类号： H01L23/5329 ,  H01L21/31144 ,  H01L21/76807 ,  H01L2221/1036 ,  H01L2924/0002

摘要： The surface of an integrated circuit, which uses reactive ion etching to pattern metal interconnection, is protected with two insulating layers on the surface. The first layer is a conventional silicon dioxide. The second layer is a photosensitive polymer which is the same as the material used for subsequent metalization of interconnection using the reactive ion etching technique. When the second layer is used, the reactive ion etching cannot attack the silicon dioxide. A trench can be cut through the two insulating layers, using a window in the photosensitive polymer as a mask, to serve as a via hole for metal to contact the substrate

摘要翻译： 使用反应离子蚀刻来形成金属互连的集成电路的表面被表面上的两个绝缘层保护。 第一层是常规的二氧化硅。 第二层是与使用反应离子蚀刻技术进行互连金属化的材料相同的感光性聚合物。 当使用第二层时，反应离子蚀刻不能侵蚀二氧化硅。 可以使用光敏聚合物中的窗口作为掩模，通过两个绝缘层切割沟槽，以用作金属与基板接触的通孔

公开(公告)号：US08178368B2

公开(公告)日：2012-05-15

申请号：US12621513

申请日：2009-11-19

申请人： Victor Seng Keong Lim ,  Rachel Yie Fang Wai ,  Fang Hong Gn ,  Liang Choo Hsia

发明人： Victor Seng Keong Lim ,  Rachel Yie Fang Wai ,  Fang Hong Gn ,  Liang Choo Hsia

IPC分类号： G06F17/50

CPC分类号： H01L22/12

摘要： A method of forming a device is disclosed. The method includes providing a substrate on which the device is formed. It also includes forming a test cell on the substrate. The test cell includes a defect programmed into the cell to facilitate defect detection.

摘要翻译： 公开了一种形成装置的方法。 该方法包括提供其上形成有该器件的衬底。 它还包括在衬底上形成测试电池。 测试单元包括编程到单元中以便于缺陷检测的缺陷。

公开(公告)号：US20120086468A1

公开(公告)日：2012-04-12

申请号：US12925031

申请日：2010-10-12

申请人： Zhihong Mai ,  Pik Kee Tan ,  Guo Chang Man ,  Jeffrey Lam ,  Liang Choo Hsia

发明人： Zhihong Mai ,  Pik Kee Tan ,  Guo Chang Man ,  Jeffrey Lam ,  Liang Choo Hsia

IPC分类号： H03K19/003

CPC分类号： G01R31/311 ,  G01R31/001 ,  G01R31/318511

摘要： According to an embodiment of the disclosure, a method verifies bitmap information or test data information for a semiconductor device. The method places a defect on a semiconductor device at an actual defect location using a laser to physically damage the semiconductor device. A logical address associated with the defect is detected and bitmap information or test data information is reviewed to determine an expected location corresponding to the logical address. Then, the accuracy of the bitmap information or the test data information is determined by comparing the actual defect location with the expected location. A deviation between the two indicates an inaccuracy.

摘要翻译： 根据本公开的实施例，一种方法验证半导体器件的位图信息或测试数据信息。 该方法使用激光将实际缺陷位置的缺陷放置在半导体器件上以物理地损坏半导体器件。 检测与缺陷相关联的逻辑地址，并且对位图信息或测试数据信息进行检查以确定对应于逻辑地址的期望位置。 然后，通过将实际缺陷位置与预期位置进行比较来确定位图信息或测试数据信息的准确度。 两者之间的偏差表示不准确。