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    PERIPHERAL DEVICE ASSISTANCE IN REDUCING CPU POWER CONSUMPTION
    41.
    发明申请
    PERIPHERAL DEVICE ASSISTANCE IN REDUCING CPU POWER CONSUMPTION 审中-公开
    外围设备协助降低CPU功耗

    公开(公告)号：US20150370309A1

    公开(公告)日：2015-12-24

    申请号：US14745549

    申请日：2015-06-22

    Applicant: MELLANOX TECHNOLOGIES LTD.

    Inventor： Idan Burstein ,  Shlomo Raikin ,  Noam Bloch

    IPC: G06F1/32

    CPC classification number: G06F1/3209

    Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having multiple host resources, information regarding respective power states of the host resources. The data are selectively directed from the peripheral device to the host resources responsively to the respective power states.

    Abstract translation: 一种用于处理数据的方法包括在通过总线连接到具有多个主机资源的主机处理器的外围设备中接收关于主机资源的各自的电力状态的信息。 响应于各自的功率状态，数据被选择性地从外围设备引导到主机资源。

    STORAGE SYSTEM AND SERVER
    42.
    发明申请
    STORAGE SYSTEM AND SERVER 有权
    存储系统和服务器

    公开(公告)号：US20150261434A1

    公开(公告)日：2015-09-17

    申请号：US14215099

    申请日：2014-03-17

    Applicant: Mellanox Technologies Ltd.

    Inventor： Michael Kagan ,  Noam Bloch ,  Shlomo Raikin ,  Yaron Haviv ,  Idan Burstein

    IPC: G06F3/06 ,  H04L29/08

    CPC classification number: G06F13/28 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0688 ,  G06F13/4221 ,  G06F15/17331 ,  H04L67/10 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A data storage system includes a storage server, including non-volatile memory (NVM) and a server network interface controller (NIC), which couples the storage server to a network. A host computer includes a host central processing unit (CPU), a host memory and a host NIC, which couples the host computer to the network. The host computer runs a driver program that is configured to receive, from processes running on the host computer, commands in accordance with a protocol defined for accessing local storage devices connected to a peripheral component interface bus of the host computer, and upon receiving a storage access command in accordance with the protocol, to initiate a remote direct memory access (RDMA) operation to be performed by the host and server NICs so as to execute on the storage server, via the network, a storage transaction specified by the command.

    Abstract translation: 数据存储系统包括存储服务器，其包括非易失性存储器（NVM）和将存储服务器耦合到网络的服务器网络接口控制器（NIC）。 主计算机包括主机中央处理单元（CPU），主机存储器和主机NIC，其将主计算机耦合到网络。 主计算机运行驱动程序，其被配置为从主机计算机上运行的进程接收根据为访问连接到主计算机的外围组件接口总线的本地存储设备而定义的协议的命令，以及在接收到存储器 访问命令，以启动由主机和服务器NIC执行的远程直接存储器访问（RDMA）操作，以便经由网络在存储服务器上执行由该命令指定的存储事务。

    Data processing unit with transparent root complex
    46.
    发明授权
    Data processing unit with transparent root complex 有权

    公开(公告)号：US12117948B2

    公开(公告)日：2024-10-15

    申请号：US17976909

    申请日：2022-10-31

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Liran Liss ,  Rabia Loulou ,  Idan Burstein ,  Tzuriel Katoa

    IPC: G06F13/28 ,  G06F13/42

    CPC classification number: G06F13/28 ,  G06F13/4221

    Abstract: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.

    Computational accelerator for storage operations
    48.
    发明授权
    Computational accelerator for storage operations 有权

    公开(公告)号：US11765079B2

    公开(公告)日：2023-09-19

    申请号：US17973962

    申请日：2022-10-26

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Boris Pismenny ,  Miriam Menes ,  Idan Burstein ,  Liran Liss ,  Noam Bloch ,  Arie Shahar

    IPC: H04L45/00 ,  H04L45/42 ,  G06F11/10 ,  H04L69/163 ,  H04L69/22

    CPC classification number: H04L45/566 ,  G06F11/1004 ,  H04L45/38 ,  H04L45/42 ,  H04L69/163 ,  H04L69/22

    Abstract: A method includes detecting, by an accelerator of a networking device, a serial number of a first data packet is out of order with respect to a previous data packet within a first flow of data packets associated with a packet communication network, wherein the serial number is assigned to the first data packet according to a transport protocol. The method includes reconstructing context data associated with the first flow of data packets, wherein the context data comprises encoding information for encoding of data records containing data conveyed in payloads of data packets in the first flow of data packets according to a storage protocol. The method includes using, by the accelerator, the reconstructed context data in processing a data record associated with a second data packet within the first flow, wherein the second data packet is subsequent to the first data packet in the first flow of data packets.

    Secure and efficient distributed processing
    49.
    发明公开
    Secure and efficient distributed processing 审中-公开

    公开(公告)号：US20230185606A1

    公开(公告)日：2023-06-15

    申请号：US17899648

    申请日：2022-08-31

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Miriam Menes ,  Liran Liss ,  Noam Bloch ,  Idan Burstein ,  Boris Pismenny ,  Ariel Shahar

    IPC: G06F9/48 ,  G06F9/50 ,  G06F9/38

    CPC classification number: G06F9/4881 ,  G06F9/5027 ,  G06F9/5072 ,  G06F9/3877

    Abstract: In one embodiment, a secure distributed processing system includes nodes connected over a network, and configured to process tasks, each respective one of the nodes including a respective processor to process data of respective ones of the tasks, and a respective network interface controller to connect to other nodes over the network, store task master keys for use in computing communication keys for securing data transfer over the network for respective ones of the tasks, compute respective task and node-pair specific communication keys for securing communication with respective ones of the nodes over the network for respective ones of the tasks responsively to respective ones of the task master keys and node-specific data of respective node pairs, and securely communicate the processed data of the respective ones of the tasks with the respective ones of the nodes over the network responsively to the respective task and node-pair specific communication keys.

    Zero-copy processing
    50.
    发明申请
    Zero-copy processing 有权

    公开(公告)号：US20230099304A1

    公开(公告)日：2023-03-30

    申请号：US17488362

    申请日：2021-09-29

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Haggai Eran ,  Liran Liss ,  Yuval Shpigelman ,  Idan Burstein

    IPC: G06F3/06

    Abstract: In one embodiment, a system includes a peripheral device including a memory access interface to receive from a host device headers of packets, while corresponding payloads of the packets are stored in a host memory of the host device, and descriptors being indicative of respective locations in the host memory at which the corresponding payloads are stored, a data processing unit memory to store the received headers and the descriptors without the payloads of the packets, and a data processing unit to process the received headers, wherein the peripheral device is configured, upon completion of the processing of the received headers by the data processing unit, to fetch the payloads of the packets over the memory access interface from the respective locations in the host memory responsively to respective ones of the descriptors, and packet processing circuitry to receive the headers and payloads of the packets, and process the packets.

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