公开(公告)号：US20180012660A1

公开(公告)日：2018-01-11

申请号：US15669311

申请日：2017-08-04

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/04 ,  G11C16/16 ,  G11C11/56 ,  G11C16/08 ,  H01L27/105 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  H01L27/1052 ,  H01L27/115 ,  H01L28/00

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US20170365343A1

公开(公告)日：2017-12-21

申请号：US15690862

申请日：2017-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Akira Goda ,  Mason A. Jones

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3427

Abstract: A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected memory string of the memory device, discharging the boosted channels of the memory cells in the selected memory string, and programming a selected memory cell in the selected memory string after discharging the boosted channels in the selected memory string.

公开(公告)号：US09793282B2

公开(公告)日：2017-10-17

申请号：US14925589

申请日：2015-10-28

Applicant: Micron Technology, Inc.

Inventor： Charles H. Dennison ,  Akira Goda ,  John Hopkins ,  Fatma Arzum Simsek-Ege ,  Krishna K. Parat

IPC: H01L27/11556 ,  H01L29/66 ,  H01L27/11578 ,  H01L21/28

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L27/11578 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833

Abstract: Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A floating gate is formed between the first tier of dielectric material and the second tier of dielectric material, wherein the floating gate includes a protrusion extending towards the control gate. A charge blocking structure is formed between the floating gate and the control gate, wherein at least a portion of the charge blocking structure wraps around the protrusion.

公开(公告)号：US09779829B2

公开(公告)日：2017-10-03

申请号：US14943541

申请日：2015-11-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christian Caillat ,  Akira Goda

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/34 ,  G11C16/14 ,  G11C16/16

CPC classification number: G11C16/3445 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/16

Abstract: A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device during an erase operation. The memory block of memory cells includes a plurality of memory segments and a corresponding plurality of first select gate control lines. Each memory segment includes a plurality of memory sub-blocks that share a respective one of the first select gate control lines. The method includes applying a first bias voltage to the respective first select gate control line of a first one of the memory segments that has failed an erase verify operation to facilitate erasing the first memory segment during the erase operation, and applying a second bias voltage different from the first bias voltage to the respective first select gate control line of a second one of the memory segments that has passed the erase verify operation to facilitate inhibiting erasing of the second memory segment during the erase operation.

公开(公告)号：US09741737B1

公开(公告)日：2017-08-22

申请号：US15130803

申请日：2016-04-15

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L23/5226 ,  H01L27/1157 ,  H01L28/00

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US09728266B1

公开(公告)日：2017-08-08

申请号：US15205574

申请日：2016-07-08

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C16/16

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  H01L27/1052 ,  H01L27/115 ,  H01L28/00

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US20170178737A1

公开(公告)日：2017-06-22

申请号：US15437584

申请日：2017-02-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carmine Miccoli ,  Christian Caillat ,  Akira Goda

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3459 ,  G11C2211/5622

Abstract: First memory cells are programmed to an intermediate level from a lowest level, corresponding to a lowest data state, where the first memory cells are to be programmed from the intermediate level to levels other than the lowest level. The first memory cells are not read or verified at the intermediate level. Different first memory cells of the first memory cells that are programmed to the intermediate level are respectively programmed to different levels of the levels other than the lowest level from the intermediate level. A second memory cell is programmed to a lower level than the different levels of the levels other than the lowest level from the lowest level while the different first memory cells are respectively programmed to the different levels of the levels other than the lowest level from the intermediate level.

公开(公告)号：US20160351253A1

公开(公告)日：2016-12-01

申请号：US14724945

申请日：2015-05-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carmine Miccoli ,  Christian Caillat ,  Akira Goda

IPC: G11C11/56 ,  G11C16/34

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3459 ,  G11C2211/5622

Abstract: Embodiments of methods and memory devices for performing the methods are disclosed. In an embodiment, one such method includes programming all memory cells that are to be respectively programmed to different levels other than a lowest level, corresponding to a lowest data state, to an intermediate level from the lowest level and respectively programming all the memory cells that are to be respectively programmed to the different levels other than the lowest level to the different levels other than the lowest level from the intermediate level.

Abstract translation: 公开了用于执行方法的方法和存储装置的实施例。 在一个实施例中，一种这样的方法包括将所有存储器单元编程为分别被编程到除了最低数据状态的最低级别之外的不同级别，从最低级别编程到中间级别，并分别编程所有存储器单元 分别被编程到不同于最低级别的不同级别，而不是从中间级别的最低级别以外的不同级别。

公开(公告)号：US09484101B2

公开(公告)日：2016-11-01

申请号：US14822083

申请日：2015-08-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Pranav Kalavade ,  Akira Goda ,  Tommaso Vali ,  Violante Moschiano

IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459

Abstract: Methods of programming memories include applying a first plurality of programming pulses to the group of memory cells to program first data to the group of memory cells, determining an upper limit of a resulting threshold voltage distribution for the group of memory cells following a particular programming pulse of the first plurality of programming pulses, and applying a second plurality of programming pulses to the group of memory cells to program second data to the group of memory cells, wherein a characteristic of at least one of the programming pulses of the second plurality of programming pulses is at least partially based on the determined upper limit of the threshold voltage distribution. Methods of programming memories further include programming information indicative of usage of memory cells of a page of memory cells to the page of memory cells during a portion of a programming operation.

Abstract translation: 编程存储器的方法包括将第一多个编程脉冲施加到存储器单元组以将第一数据编程到存储器单元组，确定特定编程脉冲之后的存储器单元组的结果阈值电压分布的上限 的第一多个编程脉冲，并且将第二多个编程脉冲施加到该组存储器单元以将第二数据编程到该组存储器单元，其中第二组编程脉冲中的至少一个编程脉冲的特性 脉冲至少部分地基于所确定的阈值电压分布的上限。 编程存储器的方法还包括在编程操作的一部分期间指示存储器单元的页面的存储器单元的使用的编程信息到存储器单元的页面。

公开(公告)号：US20160284728A1

公开(公告)日：2016-09-29

申请号：US15174478

申请日：2016-06-06

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: H01L27/115 ,  G11C16/26 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3445 ,  H01L21/02178 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

Abstract translation: 一些实施例包括具有多层存储器单元和相关控制门的装置和方法。 一种方法包括形成具有交替的导体材料和电介质材料的第一甲板和包含延伸穿过导体材料和电介质材料的材料的孔。 所述方法还可以包括在所述孔的扩大部分中形成牺牲材料并在所述第一甲板上形成第二层记忆单元。 描述附加的装置和方法。