中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

60 records (took 0.019 seconds)

    APPARATUSES AND METHODS FOR A MEMORY DIE ARCHITECTURE INCLUDING AN INTERFACE MEMORY
    43.
    发明申请
    APPARATUSES AND METHODS FOR A MEMORY DIE ARCHITECTURE INCLUDING AN INTERFACE MEMORY 有权
    包含界面记忆的记忆体建筑的装置和方法

    公开(公告)号：US20160070504A1

    公开(公告)日：2016-03-10

    申请号：US14942701

    申请日：2015-11-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Dean K. Nobunaga ,  Ali Feiz Zarrin Ghalam ,  Xiaojiang Guo ,  Eric N. Lee

    IPC: G06F3/06 ,  G06F13/40 ,  G06F12/08

    CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0683 ,  G06F12/0802 ,  G06F12/0893 ,  G06F13/1684 ,  G06F13/4068 ,  G06F2212/1016 ,  G06F2212/3042 ,  G11C5/066 ,  G11C7/1048 ,  G11C8/12 ,  G11C11/00

    Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus, The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.

    Abstract translation: 本文公开了用于减小数据总线上的电容的装置和方法。 根据一个或多个所描述的实施例，装置可以包括耦合到内部数据总线和命令和地址总线的多个存储器，每个存储器被配置为在命令和地址总线上接收命令。 多个存储器中的一个可以耦合到外部数据总线。多个存储器中的一个存储器可以被配置为当命令包括程序命令时将程序数据提供给内部数据总线，并且多个存储器中的另一个是 目标存储器，并且可以被配置为当命令包括读取命令并且多个存储器中的另一个是读取命令的目标存储器时，向外部数据总线提供读取数据。

    DEVICES AND SYSTEMS INCLUDING ENABLING CIRCUITS
    44.
    发明申请
    DEVICES AND SYSTEMS INCLUDING ENABLING CIRCUITS 有权
    包括启用电路的设备和系统

    公开(公告)号：US20140198586A1

    公开(公告)日：2014-07-17

    申请号：US14216528

    申请日：2014-03-17

    Applicant: Micron Technology, Inc.

    Inventor： Toru Tanzawa ,  Ali Feiz Zarrin Ghalam

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/22 ,  G11C5/143 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093

    Abstract: Examples of devices and systems including enabling circuits are described. Two voltage supplies may be used to operate different portions of the devices, including peripheral circuits and I/O circuits. When the voltage supply to the peripheral circuits of one or more devices is disabled, the I/O circuits of that device may be disabled. In some examples, power may advantageously be saved in part by eliminating or reducing a DC current path through the I/O circuits.

    Abstract translation: 描述包括使能电路的设备和系统的示例。 可以使用两个电压源来操作设备的不同部分，包括外围电路和I / O电路。 当一个或多个器件的外围电路的电源被禁止时，该器件的I / O电路可能被禁止。 在一些示例中，可以通过消除或减少通过I / O电路的DC电流路径来部分地节省功率。

    Data burst suspend mode using multi-level signaling
    45.
    发明授权
    Data burst suspend mode using multi-level signaling 有权

    公开(公告)号：US12111781B2

    公开(公告)日：2024-10-08

    申请号：US18119576

    申请日：2023-03-09

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Leonid Minz ,  Yoav Weinberg ,  Ali Feiz Zarrin Ghalam ,  Luigi Pilolli

    IPC: G06F13/30 ,  G06F13/16

    CPC classification number: G06F13/30 ,  G06F13/1668

    Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.

    DATA BURST SUSPEND MODE USING MULTI-LEVEL SIGNALING
    48.
    发明公开
    DATA BURST SUSPEND MODE USING MULTI-LEVEL SIGNALING 审中-公开

    公开(公告)号：US20230289306A1

    公开(公告)日：2023-09-14

    申请号：US18119576

    申请日：2023-03-09

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Leonid Minz ,  Yoav Weinberg ,  Ali Feiz Zarrin Ghalam ,  Luigi Pilolli

    IPC: G06F13/30 ,  G06F13/16

    CPC classification number: G06F13/30 ,  G06F13/1668

    Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.

    DATA BUS DUTY CYCLE DISTORTION COMPENSATION
    49.
    发明申请
    DATA BUS DUTY CYCLE DISTORTION COMPENSATION 有权

    公开(公告)号：US20220138120A1

    公开(公告)日：2022-05-05

    申请号：US16949510

    申请日：2020-10-30

    Applicant: Micron Technology, Inc.

    Inventor： Guan Wang ,  Ali Feiz Zarrin Ghalam ,  Chin-Yu Chen ,  Jongin Kim

    IPC: G06F13/16 ,  G11C16/32 ,  H03K3/017

    Abstract: An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

    Systems and methods involving write training to improve data valid windows
    50.
    发明授权
    Systems and methods involving write training to improve data valid windows 有权

    公开(公告)号：US11211104B2

    公开(公告)日：2021-12-28

    申请号：US17092046

    申请日：2020-11-06

    Applicant: Micron Technology, Inc.

    Inventor： Agatino Massimo Maccarrone ,  Luigi Pilolli ,  Ali Feiz Zarrin Ghalam ,  Chin Yu Chen

    IPC: G11C8/00 ,  G11C7/22 ,  G11C7/10

    Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.

Patent Agency Ranking