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公开(公告)号：US11043278B2
公开(公告)日：2021-06-22
申请号：US17017291
申请日：2020-09-10
Applicant: Micron Technology, Inc.
Inventor： Ashutosh Malshe , Kishore Kumar Muchherla , Harish Reddy Singidi , Peter Sean Feeley , Sampath Ratnam , Kulachet Tanpairoj , Ting Luo
Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
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公开(公告)号：US20210149564A1
公开(公告)日：2021-05-20
申请号：US16685300
申请日：2019-11-15
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Ankit Vinod Vashi , Xiangang Luo , Jianmin Huang
IPC: G06F3/06
Abstract: Techniques disclosed herein can be used to improve cross-temperature coverage of memory devices and improve memory device reliability in cross-temperature conditions. More specifically, a memory trim set can be selected from multiple candidate memory trim sets when performing a memory operation (such as a memory write operation), based on a temperature metric and a P/E cycle metric for the memory device. The candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation. The temperature metric can be indicative of a temperature of at least a region of the memory device (e.g., the entire device, a memory plane, a memory block, etc.), and the P/E cycle metric can be indicative of a number of P/E cycles performed by the memory device within a selected time interval.
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公开(公告)号：US10325670B2
公开(公告)日：2019-06-18
申请号：US16129422
申请日：2018-09-12
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Scott Anthony Stoller , Preston Thomson , Devin Batutis , Harish Reddy Singidi , Kulachet Tanpairoj
Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.
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公开(公告)号：US20250111886A1
公开(公告)日：2025-04-03
申请号：US18979331
申请日：2024-12-12
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Murong Lang , Zhenming Zhou , Ting Luo
Abstract: Methods, systems, and devices for read window management in a memory system are described. A memory system may determine, for a set of memory cells, a first value for a read window that is associated with a set of one or more threshold voltages each representing a different multi-bit value. The memory system may then use the first value for the read window to predict a second value for the read window. Based on the second value for the read window, the memory system may predict an error rate for the set of memory cells. The memory system may then set a value for an offset for a threshold voltage of the set of one or more threshold voltages based on the error rate.
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公开(公告)号：US20250104779A1
公开(公告)日：2025-03-27
申请号：US18782517
申请日：2024-07-24
Applicant: Micron Technology, Inc.
Inventor： Yu-Chung Lien , Ting Luo , Zhenming Zhou
Abstract: Methods, systems, and devices for a ganged read operation for multiple sub-blocks are described. The method may include writing a respective first logic state to each memory cell of a set of memory portions and biasing a first word line and a second word line to a first voltage. In some examples, the first word line may correspond to a first memory portion and the second word line may correspond to a second memory portion. Further, the method may include applying a first read pulse to the first word line and a second read pulse to the second word line and reading a second logic state from one or more memory cells of the first memory portion and the second memory portion. Further, the method may include validating the write operation based on reading the second logic state from the memory cells of the first memory portion and the second memory portion.
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Patent Agency Ranking
公开(公告)号：US20240370181A1
公开(公告)日：2024-11-07
申请号：US18651781
申请日：2024-05-01
Applicant: Micron Technology, Inc.
Inventor： Yuqi Zhu , Guang Hu , Ting Luo , Xiangang Luo
IPC: G06F3/06
Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to dynamically allocate blocks from a free block pool. The controller generates a free block pool that includes a collection of full blocks and a collection of partial good blocks (PGBs) of a set of memory components, a size of a full block in the collection of full blocks corresponding to a combination of two or more PGBs of the collection of PGBs. The controller receives a request to write data. The controller allocates an individual full block from the collection of full blocks or an individual PGB from the collection of PGBs based on determining whether the request to write the data has been received from the host device or the controller of the memory sub-system.
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公开(公告)号：US12112819B2
公开(公告)日：2024-10-08
申请号：US18376198
申请日：2023-10-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Tomoko Ogura Iwasaki , Ting Luo , Luyen Vu
CPC classification number: G11C29/42 , G11C7/1069 , G11C7/1096 , G11C29/12005 , G11C29/4401
Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.
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公开(公告)号：US20240168654A1
公开(公告)日：2024-05-23
申请号：US18504985
申请日：2023-11-08
Applicant: Micron Technology, Inc.
Inventor： Luca Porzio , Ting Luo , Ciro Feliciano , Giuseppe D'Eliseo
IPC: G06F3/06 , G06F12/1009
CPC classification number: G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F12/1009
Abstract: Methods, systems, and devices for data block refresh during read access are described. In some instances, when an access command (e.g., a read command) is received, a memory system may determine if the associated block is a PSA block. If the block is PSA block, its data may be provided to a host system to satisfy the read command and the block may either be refreshed or may be designated to be refreshed. For example, the block may be refreshed by copying its data to a write cache and writing the data from the cache to a new block. In other instances, an LBA of the block may be stored (e.g., designated) and the LBA may be refreshed when the memory system is idle.
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公开(公告)号：US11934690B2
公开(公告)日：2024-03-19
申请号：US18105043
申请日：2023-02-02
Applicant: Micron Technology, Inc.
Inventor： Tao Liu , Ting Luo , Jianmin Huang
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679 , G11C16/349
Abstract: A method includes determining a first memory access count threshold for a first word line of a block of memory cells and determining a second memory access count threshold for a second word line of the block of memory cells. The second memory access count threshold can be greater than the first memory access count threshold. The method can further include incrementing a memory block access count corresponding to the block of memory cells that includes the first word line and the second word line in response to receiving a memory access command and refreshing the first word line when the memory block access count corresponding to the block of memory cells is equal to the first memory access count threshold.
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公开(公告)号：US11798647B2
公开(公告)日：2023-10-24
申请号：US17681976
申请日：2022-02-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Tomoko Ogura Iwasaki , Ting Luo , Luyen Vu
CPC classification number: G11C29/42 , G11C7/1069 , G11C7/1096 , G11C29/12005 , G11C29/4401
Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.
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