公开(公告)号：US11416154B2

公开(公告)日：2022-08-16

申请号：US17123472

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US10671479B2

公开(公告)日：2020-06-02

申请号：US16105305

申请日：2018-08-20

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Walter Di Francesco ,  Luca De Santis ,  Giovanni Santin

IPC: H03M13/00 ,  G06F11/10 ,  G11C29/52 ,  H03M13/37 ,  G11C29/02 ,  H03M13/29 ,  H03M13/11 ,  G11C29/04 ,  H03M13/45

Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

公开(公告)号：US20190286328A1

公开(公告)日：2019-09-19

申请号：US16428011

申请日：2019-05-31

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US10359963B2

公开(公告)日：2019-07-23

申请号：US15532886

申请日：2017-01-23

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F3/064 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1021 ,  G06F2212/2022 ,  G06F2212/7201

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US10055293B2

公开(公告)日：2018-08-21

申请号：US15583678

申请日：2017-05-01

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Walter Di Francesco ,  Luca De Santis ,  Giovanni Santin

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/37 ,  G11C29/02 ,  G11C29/52 ,  H03M13/11 ,  G11C29/04 ,  H03M13/45

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/1076 ,  G11C29/02 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/2906 ,  H03M13/3715 ,  H03M13/45

Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

公开(公告)号：US12282669B2

公开(公告)日：2025-04-22

申请号：US18621747

申请日：2024-03-29

Applicant: Micron Technology, Inc.

Inventor： Luca Nubile ,  Walter Di Francesco ,  Fumin Gu ,  Ali Mohammadzadeh ,  Biagio Iorio ,  Liang Yu

IPC: G06F3/06

Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array. The control logic allocates power to one or more prioritized processing threads, of a plurality of processing threads that access the memory array, based on a value of a priority ring counter. The control logic starts a timer in response to detecting allocation of the power to a non-prioritized processing thread of the plurality of processing threads. While the timer is running, the control logic increments the priority ring counter before each power management cycle and prioritizes allocation of the power to the one or more prioritized processing threads located within a subset of the plurality of processing threads corresponding to a value of the priority ring counter.

公开(公告)号：US20250069636A1

公开(公告)日：2025-02-27

申请号：US18939609

申请日：2024-11-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yankang He ,  Walter Di Francesco ,  Luca Nubile ,  Chang Siau

IPC: G11C11/406 ,  G11C11/4072 ,  G11C11/4094

Abstract: One example of a memory device includes an array of flash memory cells, an array of Dynamic Random Access Memory (DRAM) memory cells, and a controller. The controller is configured to execute first instructions stored in the array of DRAM memory cells to access the array of flash memory cells.

公开(公告)号：US12205653B2

公开(公告)日：2025-01-21

申请号：US18083304

申请日：2022-12-16

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Shyam Sunder Raghunathan ,  Walter Di Francesco

IPC: G11C16/32 ,  G11C16/08 ,  G11C16/10

Abstract: A memory device includes an array of memory cells arranged in sub-blocks. Memory cells of a sub-block are coupled to a pillar of the array and are associated with multiple wordlines. To perform a read operation, control logic coupled with the array performs operations including: tracking a length of time that a selected wordline takes to reach a pass voltage before being able to read data from a memory cell associated with the selected wordline; in response to the length of time satisfying a first threshold criterion, causing a first delay time to pass before reading the data; and in response to the length of time satisfying a second threshold criterion that is longer than the first threshold criterion, causing a second delay time to pass before reading the data, the second delay time being longer than the first delay time.

公开(公告)号：US12094547B2

公开(公告)日：2024-09-17

申请号：US17893364

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Ali Mohammadzadeh ,  Walter Di Francesco ,  Dheeraj Srinivasan

IPC: G11C7/10 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C7/1039 ,  G11C16/102 ,  G11C16/26

Abstract: Described are systems and methods for implementing continuous memory programming operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of conductive lines; and a controller coupled to the memory array. The controller performs operations comprising: performing a memory programming operation with respect to a set of memory cells of the memory array, wherein the memory programming operation comprises a sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells; responsive to receiving a command to perform a memory access operation, suspending the memory programming operation after performing a current programming pulse of the sequence of programming pulses, wherein the current programming pulse is performed at a first voltage level; initiating the memory access operation; and resuming the memory programming operation by performing a next programming pulse at a second voltage level that exceeds the first voltage level.

公开(公告)号：US20240281378A1

公开(公告)日：2024-08-22

申请号：US18649582

申请日：2024-04-29

Applicant: Micron Technology, Inc.

Inventor： Umberto Siciliani ,  Violante Moschiano ,  Walter Di Francesco

IPC: G06F12/0842 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/30 ,  G11C16/34

CPC classification number: G06F12/0842 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/30 ,  G11C16/3459 ,  G06F2212/1024

Abstract: A memory device includes a page buffer with multiple registers and a memory array, configured as single-level cell (SLC) memory, including a set of sub-blocks coupled with the page buffer. Control logic is operatively coupled with the page buffer and causes a first page of SLC data to be stored in the multiple registers. The control logic causes a subsequent page of the SLC data to be stored in the multiple registers. The control logic causes the subsequent page and the first page of the SLC data stored in the multiple registers to be concurrently programmed to the set of sub-blocks. The control logic causes at least some of the operations for programming the first page and the subsequent page to the set of sub-blocks to be performed in parallel.