公开(公告)号：US09184096B2

公开(公告)日：2015-11-10

申请号：US13798275

申请日：2013-03-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Guan-Ru Lee ,  Erh-Kun Lai

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/115

CPC classification number: H01L21/823878 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor structure and a manufacturing method for the same are provided. The method includes following steps. A first gate structure is formed on a substrate in a first region. A protecting layer is formed covering the first gate structure. A second gate structure is formed on the substrate in second region exposed by the protecting layer and adjacent to the first region.

Abstract translation: 提供了一种半导体结构及其制造方法。 该方法包括以下步骤。 第一栅极结构形成在第一区域中的衬底上。 形成覆盖第一栅极结构的保护层。 第二栅极结构形成在由保护层露出并邻近第一区域的第二区域中的衬底上。

公开(公告)号：US09123778B2

公开(公告)日：2015-09-01

申请号：US13897702

申请日：2013-05-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Yen-Hao Shih ,  Guanru Lee

IPC: H01L21/4763 ,  H01L21/8242 ,  H01L29/40 ,  H01L21/768 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115 ,  H01L29/51 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L21/76808 ,  H01L21/28282 ,  H01L21/7682 ,  H01L21/76829 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/792

Abstract: For certain three dimensionally stacked memory devices, bit lines or word lines for memory cells are stacked in spaced apart ridge like structures arranged to extend in a first direction. In such structures, complementary wordlines or bit lines, can be damascene features between the spaced apart. The damascene conductors can be formed using double patterned masks to etch sub-lithographic sacrificial lines, forming a fill over the sacrificial lines, and then removing the sacrificial lines to leave trenches that act as the damascene molds in the fill. Then the trenches are filled with the conductor material. The 3D memory array can include dielectric charge trapping memory cells, which have a high-K blocking dielectric layer, and in which the conductor material comprises a high work function material.

Abstract translation: 对于某些三维堆叠的存储器件，用于存储器单元的位线或字线被堆叠成布置成沿第一方向延伸的间隔开的脊状结构。 在这种结构中，互补字线或位线可以是间隔开的镶嵌特征。 镶嵌导体可以使用双图案化掩模形成，以蚀刻次光刻牺牲线，在牺牲线上形成填充物，然后去除牺牲线以留下充当填充物中镶嵌模具的沟槽。 然后用导体材料填充沟槽。 3D存储器阵列可以包括具有高K阻挡介电层的介电电荷俘获存储器单元，并且其中导体材料包括高功函数材料。

公开(公告)号：US09093502B2

公开(公告)日：2015-07-28

申请号：US14086692

申请日：2013-11-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Erh-Kun Lai

IPC: G01R31/26 ,  H01L21/66 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/44 ,  H01L29/76 ,  H01L21/768 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/4916 ,  H01L21/28008 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578

Abstract: The present invention further provides a string select line (SSL) of a three-dimensional memory array, including: a dielectric substrate; an SSL structure disposed on the dielectric substrate, wherein the SSL structure includes a plurality of dielectric layers and a plurality of first conductive layers, the dielectric layers and the first conductive layers stacked alternatively; a second conductive layer covering sidewalls and a top portion of the SSL structure; and an oxide layer disposed between the first conductive layers and the second conductive layer, and contacting with the first conductive layers and the second conductive layer.

Abstract translation: 本发明还提供一种三维存储器阵列的串选择线（SSL），包括：介质衬底; 设置在所述电介质基板上的SSL结构，其中所述SSL结构包括多个电介质层和多个第一导电层，所述电介质层和所述第一导电层交替堆叠; 覆盖所述SSL结构的侧壁和顶部的第二导电层; 以及设置在所述第一导电层和所述第二导电层之间并与所述第一导电层和所述第二导电层接触的氧化物层。

公开(公告)号：US20150187694A1

公开(公告)日：2015-07-02

申请号：US14143040

申请日：2013-12-30

Applicant: Macronix International Co., Ltd.

Inventor： Erh-Kun Lai ,  Guan-Ru Lee ,  Yen-Hao Shih

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L27/105 ,  H01L21/3205 ,  H01L23/532

CPC classification number: H01L21/32133 ,  H01L21/32055 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a stacked structure, a dielectric layer, a conductive structure, a dielectric structure and a conductive plug. The stacked structure includes dielectric films and conductive films arranged alternately. The dielectric layer is between the conductive structure and a sidewall of the stacked structure. The dielectric structure is on the stacked structure and defining a through via. The conductive plug fills the through via and physically contacts one of the conductive films exposed by the through via and adjoined with the dielectric layer.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括基板，堆叠结构，电介质层，导电结构，电介质结构和导电插塞。 堆叠结构包括交替布置的介电膜和导电膜。 介电层位于导电结构和层叠结构的侧壁之间。 电介质结构在堆叠结构上并且限定通孔。 导电插塞填充通孔并物理地接触由通孔暴露并与电介质层相邻的导电膜之一。

公开(公告)号：US20150060958A1

公开(公告)日：2015-03-05

申请号：US14016308

申请日：2013-09-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shih-Hung Chen ,  Erh-Kun Lai

IPC: H01L21/28 ,  H01L29/78

CPC classification number: H01L21/28008 ,  H01L21/28282 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/78

Abstract: A semiconductor device and a manufacturing method of the same are provided. The semiconductor device includes a substrate and a stacked structure vertically formed on the substrate. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers, and the conductive layers and the insulating layers are interlaced. At least one of the conductive layers has a first doping segment having a first doping property and a second doping segment having a second doping property, the second doping property being different from the first doping property. The interface between the first doping segment and the second doping segment has a grain boundary.

Abstract translation: 提供了一种半导体器件及其制造方法。 半导体器件包括衬底和垂直形成在衬底上的堆叠结构。 层叠结构包括多个导电层和多个绝缘层，并且导电层和绝缘层交错。 导电层中的至少一个具有具有第一掺杂特性的第一掺杂区段和具有第二掺杂特性的第二掺杂区段，第二掺杂特性不同于第一掺杂特性。 第一掺杂段和第二掺杂段之间的界面具有晶界。

公开(公告)号：US20150009759A1

公开(公告)日：2015-01-08

申请号：US14165180

申请日：2014-01-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai

IPC: G11C16/06

CPC classification number: G11C16/06 ,  G11C16/0483 ,  G11C16/14 ,  H01L27/11578

Abstract: A memory includes a doped substrate well, a substrate connector coupled to the doped substrate well, and a set of interlayer connectors insulated from the doped substrate well. A series arrangement including a plurality of memory cells is coupled on a first end by a first switch to a bit line and coupled on a second end by a second switch to a source line contact pad. The source line contact pad is connected to the substrate connector and to at least one of the interlayer connectors in the set of interlayer connectors. A supply line is connected to the set of interlayer connectors. A plurality of word lines is coupled to the plurality of memory cells. Circuitry is coupled to the supply line and to the doped substrate well and configured to bias the supply line and the doped substrate well with different bias conditions.

Abstract translation: 存储器包括掺杂衬底阱，耦合到掺杂衬底阱的衬底连接器以及与掺杂衬底阱绝缘的一组层间连接器。 包括多个存储单元的串联装置在第一端上通过第一开关耦合到位线，并且在第二端上通过第二开关耦合到源极线接触焊盘。 源极线接触焊盘连接到衬底连接器和至少一个层间连接器中的层间连接器中的一个。 电源线连接到一组层间连接器。 多个字线耦合到多个存储单元。 电路耦合到电源线和掺杂衬底，并被配置为在不同的偏置条件下对供电线和掺杂衬底进行偏置。

公开(公告)号：US20140124945A1

公开(公告)日：2014-05-08

申请号：US13670669

申请日：2012-11-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Yen-Hao Shih ,  Shih-Chang Tsai

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L27/101 ,  H01L27/11568 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a stacked structure, a plurality of first conductive blocks, a plurality of first conductive layers, a plurality of second conductive layers, and a plurality of conductive damascene structures. The stacked structure, comprising a plurality of conductive strips and a plurality of insulating strips, is formed on a substrate, and the conductive strips and the insulating strips are interlaced. The first conductive blocks are formed on the stacked structure. The first conductive layers and the second conductive layers are formed on two sidewalls of the stacked structure, respectively. The conductive damascene structures are formed on two sides of the stacked structure, wherein each of the first conductive blocks is electrically connected to each of the conductive damascene structures via each of the first conductive strips and each of the second conductive strips.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括堆叠结构，多个第一导电块，多个第一导电层，多个第二导电层和多个导电镶嵌结构。 在衬底上形成包括多个导电条和多个绝缘条的堆叠结构，并且导电条和绝缘条交错。 第一导电块形成在堆叠结构上。 第一导电层和第二导电层分别形成在层叠结构的两个侧壁上。 导电镶嵌结构形成在堆叠结构的两侧，其中每个第一导电块经由第一导电条和每个第二导电条经由每个导电镶嵌结构电连接。

公开(公告)号：US12040406B2

公开(公告)日：2024-07-16

申请号：US17504599

申请日：2021-10-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai

IPC: H01L29/786 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/42392 ,  H01L29/6656

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a bottom dielectric layer continuously disposed on the substrate. The semiconductor structure further includes a plurality of stacks disposed on the bottom dielectric layer. Each of the stacks includes gate electrodes and semiconductor layers disposed alternately. The semiconductor structure further includes a plurality of source/drain structures disposed on the bottom dielectric layer and between the stacks. The semiconductor structure further includes a plurality of conductors landed on highest gate electrodes of the stacks.

公开(公告)号：US11916011B2

公开(公告)日：2024-02-27

申请号：US17230114

申请日：2021-04-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Hsiang-Lan Lung

IPC: H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: Memory devices are implemented within a vertical memory structure, comprising a stack of alternating layers of insulator material and word line material, with a series of alternating conductive pillars and insulating pillars disposed through stack. Data storage structures are disposed on inside surfaces of the layers of word line material at cross-points of the insulating pillars and the layers of word line material. Semiconductor channel material is disposed between the insulating pillars and the data storage structures at cross-points of the insulating pillars with the layers of word line material. The semiconductor channel material extends around an outside surface of the insulating pillars, contacting the adjacent conductive pillars on both sides to provide source/drain terminals.

公开(公告)号：US11688688B2

公开(公告)日：2023-06-27

申请号：US17249837

申请日：2021-03-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/535 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/535

Abstract: A semiconductor structure is provided. The semiconductor structure includes a staircase structure including a first stair layer and a second stair layer on the first stair layer. The first stair layer comprises a first conductive film. The semiconductor structure includes a landing pad disposed on the first conductive film. The landing pad has a first pad sidewall facing toward the second stair layer, a first lateral gap distance between an upper portion of the first pad sidewall and the second stair layer is smaller than a second lateral gap distance between a lower portion of the first pad sidewall and the second stair layer.