公开(公告)号：US07342277B2

公开(公告)日：2008-03-11

申请号：US11285763

申请日：2005-11-21

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

IPC分类号： H01L29/76

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0541

摘要： A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.

公开(公告)号：US20080151603A1

公开(公告)日：2008-06-26

申请号：US12072971

申请日：2008-02-28

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

IPC分类号： G11C11/34

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0541

摘要： A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.

摘要翻译： 描述了具有源电极和漏电极的晶体管。 晶体管具有至少一个电耦合在源极和漏极之间的半导体碳纳米管。 晶体管具有在碳纳米管和栅电极之间含有一个或多个量子点的栅电极和电介质材料。

公开(公告)号：US20080142786A1

公开(公告)日：2008-06-19

申请号：US11610415

申请日：2006-12-13

申请人： Suman Datta ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Marko Radosavljevic

发明人： Suman Datta ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Marko Radosavljevic

IPC分类号： H01L29/12

CPC分类号： H01L29/7783 ,  H01L29/517

摘要： A group III-V material device may have a capping layer on a barrier region, which may provide a high quality interface for a high-k gate dielectric. This may improve the performance of the device by reducing gate leakage and preserve the high-mobility properties of the quantum well channel region of the device.

摘要翻译： III-V族材料器件可以在阻挡区域上具有覆盖层，这可为高k栅极电介质提供高质量的界面。 这可以通过减少栅极泄漏并且保持器件的量子阱沟道区域的高迁移率特性来改善器件的性能。

公开(公告)号：US20090283496A1

公开(公告)日：2009-11-19

申请号：US11391920

申请日：2006-03-28

申请人： Marko Radosavljevic ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Suman Datta

发明人： Marko Radosavljevic ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Suman Datta

IPC分类号： B44C1/22 ,  B05D5/12

CPC分类号： B82Y40/00 ,  B82Y30/00 ,  C01B32/162

摘要： Embodiments of the invention include apparatuses and methods relating to directed carbon nanotube growth using a patterned layer. In some embodiments, the patterned layer includes an inhibitor material that directs the growth of carbon nanotubes.

摘要翻译： 本发明的实施例包括与使用图案化层的定向碳纳米管生长相关的装置和方法。 在一些实施方案中，图案化层包括引导碳纳米管生长的抑制剂材料。

公开(公告)号：US20090140301A1

公开(公告)日：2009-06-04

申请号：US11947157

申请日：2007-11-29

申请人： Mantu K. Hudait ,  Marko Radosavljevic ,  Suman Datta

发明人： Mantu K. Hudait ,  Marko Radosavljevic ,  Suman Datta

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/20 ,  H01L21/28575 ,  H01L29/452 ,  H01L29/456

摘要： Reducing contact resistance in p-type field effect transistors is generally described. In one example, an apparatus includes a first semiconductor substrate, a first noble metal film including palladium (Pd) coupled with the first semiconductor substrate, a second noble metal film including platinum (Pt) coupled with the first noble metal film, and a third metal film including an electrically conductive metal coupled with the second noble metal film, wherein the first, second, and third metal films form one or more contacts having reduced specific contact resistance between the first semiconductor substrate and the one or more contacts.

摘要翻译： 通常描述在p型场效应晶体管中降低接触电阻。 在一个实例中，一种装置包括第一半导体衬底，包括与第一半导体衬底耦合的钯（Pd）的第一贵金属膜，包含与第一贵金属膜耦合的铂（Pt）的第二贵金属膜，以及第三贵金属膜 金属膜包括与第二贵金属膜耦合的导电金属，其中第一，第二和第三金属膜形成一个或多个具有降低的第一半导体衬底和一个或多个触点之间的比接触电阻的触点。

公开(公告)号：US20070114593A1

公开(公告)日：2007-05-24

申请号：US11285763

申请日：2005-11-21

申请人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

发明人： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0541

摘要： A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.

摘要翻译： 描述了具有源电极和漏电极的晶体管。 晶体管具有至少一个电耦合在源极和漏极之间的半导体碳纳米管。 晶体管具有在碳纳米管和栅电极之间含有一个或多个量子点的栅电极和电介质材料。

公开(公告)号：US10050015B2

公开(公告)日：2018-08-14

申请号：US15121759

申请日：2014-03-27

申请人： Ravi Pillarisetty ,  Sansaptak Dasgupta ,  Niloy Mukherjee ,  Brian S. Doyle ,  Marko Radosavljevic ,  Han Wui Then

发明人： Ravi Pillarisetty ,  Sansaptak Dasgupta ,  Niloy Mukherjee ,  Brian S. Doyle ,  Marko Radosavljevic ,  Han Wui Then

IPC分类号： H01L29/10 ,  H01L29/12 ,  H01L25/065 ,  H01L25/00 ,  H01L29/20 ,  H01L29/24 ,  G06F1/16 ,  G09F9/30 ,  G09G3/36 ,  H01L21/8258 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L21/822 ,  H01L27/06

摘要： Embodiments of the present disclosure describe multi-device flexible systems on a chip (SOCs) and methods for making such SOCs. A multi-material stack may be processed sequentially to form multiple integrated circuit (IC) devices in a single flexible SOC. By forming the IC devices from a single stack, it is possible to form contacts for multiple devices through a single metallization process and for those contacts to be located in a common back-plane of the SOC. Stack layers may be ordered and processed according to processing temperature, such that higher temperature processes are performed earlier. In this manner, intervening layers of the stack may shield some stack layers from elevated processing temperatures associated with processing upper layers of the stack. Other embodiments may be described and/or claimed.

公开(公告)号：US09245989B2

公开(公告)日：2016-01-26

申请号：US13976414

申请日：2011-12-19

申请人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

发明人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC分类号： H01L29/775 ,  H01L29/66 ,  G05F3/02 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/20

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/225 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

摘要： Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, and drain and source contacts similarly coaxially wrap completely around the drain and source regions.

摘要翻译： 晶体管适用于高电压和高频工作。 纳米线垂直或水平地布置在基底上。 纳米线的纵向长度被限定为第一半导体材料的沟道区域，与沟道区域的第一端电耦合的源极区域，与沟道区域的第二端电耦合的漏极区域和外部漏极 区域设置在沟道区域和漏极区域之间。 外在漏极区具有比第一半导体更宽的带隙。 包括栅极导体和栅极绝缘体的栅极堆叠器完全同轴地包裹在沟道区域周围，并且漏极和源极触点类似地同轴地围绕漏极和源极区域包裹。

公开(公告)号：US09123567B2

公开(公告)日：2015-09-01

申请号：US13976411

申请日：2011-12-19

申请人： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

发明人： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786 ,  H01L27/12 ,  B82Y10/00 ,  H01L29/78

CPC分类号： H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

摘要翻译： 在同一衬底（例如硅）上的非均质材料如III-V族半导体材料和IV族半导体（例如Ge）共同整合的体系结构和技术。 在实施例中，采用具有交替的纳米线和牺牲层的多层非均相半导体材料堆叠以释放纳米线并允许形成完全包围纳米线晶体管的沟道区域的同轴栅极结构。 在实施例中，各个PMOS和NMOS沟道半导体材料与具有交替的Ge / III-V层的覆盖层的起始衬底共同整合。 在实施例中，单个PMOS和单独NMOS器件内的多个堆叠的纳米线的垂直积分能够为给定的布局区域提供显着的驱动电流。

公开(公告)号：US08633471B2

公开(公告)日：2014-01-21

申请号：US13032777

申请日：2011-02-23

申请人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

发明人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

IPC分类号： H01L29/12

CPC分类号： H01L29/155 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7831

摘要： Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed, which may include a modulation doped heterostructure, wherein the modulation doped heterostructure may comprise an active portion having a first bandgap and a delta doped portion having a second bandgap.

摘要翻译： 本文通常描述用于提供包括调制掺杂晶体管的三维互补金属氧化物半导体器件的装置和方法的实施例。 可以描述和要求保护其他实施例，其可以包括调制掺杂异质结构，其中调制掺杂异质结构可以包括具有第一带隙的有源部分和具有第二带隙的δ掺杂部分。