公开(公告)号：US11562791B1

公开(公告)日：2023-01-24

申请号：US17396825

申请日：2021-08-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hao T. Nguyen ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Dheeraj Srinivasan ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Aaron S. Yip ,  Yoshihiko Kamata

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56

Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.

公开(公告)号：US20220020736A1

公开(公告)日：2022-01-20

申请号：US16932098

申请日：2020-07-17

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Kunal R. Parekh ,  Akira Goda

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20210366527A1

公开(公告)日：2021-11-25

申请号：US17392924

申请日：2021-08-03

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Theodore T. Pekny

IPC: G11C8/08 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

Abstract: A memory device includes a memory array with memory blocks each having a plurality of memory cells, and one or more current monitors configured to measure current during post-deployment operation of the memory device; and a controller configured to identify a bad block within the memory blocks based on the measured current, and disable the bad block for preventing access thereof during subsequent operations of the memory device.

公开(公告)号：US11081165B2

公开(公告)日：2021-08-03

申请号：US16913115

申请日：2020-06-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip

IPC: G11C11/408 ,  G11C7/10 ,  G11C16/08 ,  G11C7/12 ,  G11C8/08 ,  G11C8/12 ,  G11C16/04 ,  G11C8/10

Abstract: Memories having block select circuitry having an output that is selectively connected to a plurality of driver circuitries, with each driver circuitry connected to a respective block of memory cells.

公开(公告)号：US20210050357A1

公开(公告)日：2021-02-18

申请号：US17087419

申请日：2020-11-02

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip

IPC: H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11575

Abstract: A microelectronic device comprises a stack structure having tiers each including a conductive structure and an insulating structure, the stack structure comprises a staircase region comprising staircase structures, a select gate contact region, and a memory array region between the staircase region and the select gate contact region; contact structures on steps of the staircase structures; string drivers coupled to the contact structures and comprising transistors underlying and within horizontal boundaries of the staircase region; a triple well structure underlying the memory array region; a select gate structure between the stack structure and the triple well structure; semiconductive pillar structures within horizontal boundaries of the memory array region and extending through the stack structure and the select gate structure to the triple well structure; and a select gate contact structure within horizontal boundaries of the select gate contact region and extending through the stack structure to the select gate structure.

公开(公告)号：US10891191B2

公开(公告)日：2021-01-12

申请号：US16352530

申请日：2019-03-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Patrick R. Khayat ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Mark A. Helm ,  Aaron S. Yip

IPC: G06F11/00 ,  G06F11/10 ,  H03M13/37 ,  H03M13/00 ,  G11C7/08 ,  G06F3/06 ,  G11C16/08 ,  G11C16/26 ,  G11C29/52 ,  H03M13/11 ,  G11C29/04 ,  H03M13/29 ,  G11C11/56 ,  G11C16/04

Abstract: An example method for determining likelihood of erroneous data bits stored in memory cells may include sensing a first plurality of memory cells based on a first sense thresholds. Responsive to sensing the first plurality of cells, a first set of probabilistic information may be associated with the first plurality of memory cells. A second plurality of memory cells may be sensed based on a second sense threshold. Responsive to sensing the second plurality of memory cells, a second set of probabilistic information may be associated with the second plurality of memory cells. An error correction operation may be performed on the first and second pluralities of memory cells based, at least in part, on the first and second values.

公开(公告)号：US20190341113A1

公开(公告)日：2019-11-07

申请号：US16516791

申请日：2019-07-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/26

Abstract: Methods of operating a memory include applying a programming pulse having a particular voltage level to a selected access line connected to a plurality of memory cells selected for programming during a programming operation, concurrently enabling for programming each memory cell of the plurality of memory cells selected for programming while applying the programming pulse, applying a subsequent programming pulse having a plurality of different voltage levels to the selected access line, and, for each group of memory cells of a plurality of groups of memory cells of the plurality of memory cells selected for programming, enabling that group of memory cells for programming while the subsequent programming pulse has a corresponding voltage level of the plurality of different voltage levels.

公开(公告)号：US20190066797A1

公开(公告)日：2019-02-28

申请号：US15687581

申请日：2017-08-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip

IPC: G11C16/14 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3445

Abstract: Methods include applying a first voltage to channel regions of a plurality of memory cells; applying a lower second voltage to each access line of a plurality of access lines coupled to the memory cells other than a first set of access lines; applying a lower third voltage to the first set of access lines while applying the first voltage and the second voltage; determining a desired voltage level of the third voltage for a subsequent set of access lines; and applying the third voltage to the subsequent set of access lines while applying the first voltage and while applying the second voltage to each access line of the plurality of access lines other than the subsequent set of access lines. Methods further include methods of determining the desired voltage level for the third voltage for each set of access lines.

公开(公告)号：US20180301195A1

公开(公告)日：2018-10-18

申请号：US16018566

申请日：2018-06-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Aaron S. Yip

IPC: G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04

Abstract: Methods of operating a memory include applying a programming pulse having a particular voltage level to a selected access line connected to a plurality of memory cells selected for programming during a programming operation, concurrently enabling for programming each memory cell of the plurality of memory cells selected for programming while applying the programming pulse, applying a subsequent programming pulse having a plurality of different voltage levels to the selected access line, and, for each group of memory cells of a plurality of groups of memory cells of the plurality of memory cells selected for programming, enabling that group of memory cells for programming while the subsequent programming pulse has a corresponding voltage level of the plurality of different voltage levels.

公开(公告)号：US20180081753A1

公开(公告)日：2018-03-22

申请号：US15267844

申请日：2016-09-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Patrick R. Khayat ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Mark A. Helm ,  Aaron S. Yip

IPC: G06F11/10 ,  H03M13/11 ,  G11C29/52 ,  G06F3/06 ,  G11C16/26 ,  G11C16/08

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G11C16/08 ,  G11C16/26 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1111 ,  H03M13/1177 ,  H03M13/2909 ,  H03M13/3723 ,  H03M13/612

Abstract: Methods and apparatuses for generating probabilistic information for error correction using current integration are disclosed. An example method comprises sensing a first plurality of memory cells based on a first sense threshold, responsive to sensing the first plurality of cells, associating a first set of probabilistic information with the first plurality of memory cells, sensing a second plurality of memory cells based on a second sense threshold, responsive to sensing the second plurality of memory cells, associating a second set of probabilistic information with the second plurality of memory cells, and performing an error correction operation on the first and second pluralities of memory cells based, at least in part, on the first and second values.