公开(公告)号：US20210027842A1

公开(公告)日：2021-01-28

申请号：US17068000

申请日：2020-10-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Silvia Beltrami ,  Angelo Visconti

IPC: G11C16/10 ,  G11C16/12 ,  G11C16/34

Abstract: Memory devices might include a controller configured to cause the memory device to apply a first plurality of incrementally increasing programming pulses to control gates of a particular plurality of memory cells selected for programming to respective intended data states, determine a first occurrence of a criterion being met, store a representation of a voltage level corresponding to a particular programming pulse in response to the first occurrence of the criterion being met, set a starting programming voltage for a second plurality of incrementally increasing programming pulses in response to the stored representation of the voltage level corresponding to the particular programming pulse, and apply the second plurality of incrementally increasing programming pulses to control gates of a different plurality of memory cells selected for programming to respective intended data states.

公开(公告)号：US10896712B2

公开(公告)日：2021-01-19

申请号：US16441806

申请日：2019-06-14

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Andrea Locatelli ,  Giorgio Servalli

IPC: G11C11/22 ,  G06F3/06

Abstract: Methods, systems, and devices for biasing techniques, such as open page biasing techniques, are described. A memory cell may be accessed during an access phase of an access operation, for example, an open page access operation. An activate pulse may be applied to the memory cell during the access phase. The memory cell may be biased to a non-zero voltage after applying the activate pulse and before a pre-charge phase. The pre-charge phase of the access phase may be initiated after biasing the memory cell to the non-zero voltage.

公开(公告)号：US10586597B2

公开(公告)日：2020-03-10

申请号：US16019631

申请日：2018-06-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Silvia Beltrami ,  Angelo Visconti

IPC: G11C16/10 ,  G11C16/12 ,  G11C16/34

Abstract: Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.

公开(公告)号：US08977929B2

公开(公告)日：2015-03-10

申请号：US13779381

申请日：2013-02-27

Applicant: Micron Technology, Inc.

Inventor： Aswin Thiruvengadam ,  Angelo Visconti ,  Mauro Bonanomi ,  Richard E. Fackenthal ,  William Melton

IPC: H03M13/00 ,  G06F11/16

CPC classification number: G06F11/1008 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0644 ,  G06F3/0673 ,  G06F3/0679 ,  G06F11/0751 ,  G06F11/1048 ,  G06F11/1666 ,  G11C7/1006 ,  G11C7/1012 ,  G11C13/0004 ,  G11C13/0069 ,  G11C16/10 ,  G11C19/00

Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.

Abstract translation: 本公开涉及通过将要编程的数据移动到存储器以避免硬错误而避免在写入时间期间的存储器中的硬错误。 在一个实现中，将数据编程到存储器阵列的方法包括获得与所选择的存储器单元相对应的错误数据，移位数据模式，使得所选存储器单元要存储的值与硬错误相关联的值匹配，以及 将移位的数据模式编程到存储器阵列，使得编程到所选择的存储器单元的值与与硬错误相关联的值匹配。

公开(公告)号：US20140293698A1

公开(公告)日：2014-10-02

申请号：US14301798

申请日：2014-06-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Silvia Beltrami ,  Angelo Visconti

IPC: G11C16/34

CPC classification number: G11C16/10 ,  G11C16/12 ,  G11C16/3459 ,  G11C16/3463 ,  G11C16/3468 ,  G11C16/3486 ,  G11C16/3495

Abstract: Certain aspects of this disclosure relate to programming an at least one flash memory cell using an at least one programming pulse with a new programming voltage having a level. The level is maintained in at least one page in a block of a flash memory controller memory, wherein the level varies as a function of a number of programming cycles applied to the at least one flash memory cell.

Abstract translation: 本公开的某些方面涉及使用具有具有电平的新编程电压的至少一个编程脉冲来编程至少一个闪存单元。 该电平被维持在闪速存储器控制器存储器的块中的至少一个页面中，其中该电平根据应用于至少一个闪存单元的编程周期的数量而变化。

公开(公告)号：US11742002B2

公开(公告)日：2023-08-29

申请号：US17550535

申请日：2021-12-14

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Daniele Balluchi ,  Giorgio Servalli

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/22

CPC classification number: G11C7/1048 ,  G11C7/222 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297

Abstract: Systems, apparatuses, and methods related to memory activation timing management are described herein. In an examples, memory activation timing management can include receiving a first command associated with a set of memory cells, activating the set of memory cells to perform a memory access responsive to the first command, pre-charging the set of memory cells associated with the first command, receiving a second command associated with the set of memory cells, determining that the set of memory cells associated with the first command is a recently activated set of the plurality of sets of memory cells, imparting a delay, and applying a sensing voltage to the set of memory cells associated with the second command to perform a memory access responsive to the second command.

公开(公告)号：US20230215495A1

公开(公告)日：2023-07-06

申请号：US17649104

申请日：2022-01-27

Applicant: Micron Technology, Inc.

Inventor： Riccardo Pazzocco ,  Angelo Visconti

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4076

CPC classification number: G11C11/4096 ,  G11C11/4093 ,  G11C11/4087 ,  G11C11/4076

Abstract: Methods, systems, and devices for managing memory based on access duration are described. A memory device may include a first set of memory cells resilient against access durations of a first duration and a second set of memory cells resilient against access durations of a shorter duration. A command for accessing the memory device may be received. The command may be associated with an access duration. Whether to access, as part of executing the command, the first set of memory cells or the second set of memory cells may be determined based on the access duration. The first set of memory cells may be accessed, as part of executing the command, based on the access duration being greater than a threshold duration. Or the second set of memory cells may be accessed based on the access duration being less than or equal to the threshold duration.

公开(公告)号：US11693735B2

公开(公告)日：2023-07-04

申请号：US17714777

申请日：2022-04-06

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal ,  Angelo Visconti

IPC: G06F11/10 ,  G06F13/28 ,  G06F11/30 ,  G06F11/16 ,  G11C11/22 ,  G11C11/4091

CPC classification number: G06F11/1068 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/4091

Abstract: Methods, systems, and devices for erasure decoding for a memory device are described. In accordance with the described techniques, a memory device may be configured to identify conditions associated with an erasure, a possible erasure, or an otherwise indeterminate logic state (e.g., of a memory cell, of an information position of a codeword). Such an identification may be used to enhance aspects of error handling operations, including those that may be performed at the memory device or a host device (e.g., error handling operations performed at a memory controller external to the memory device). For example, error handling operations may be performed using speculative codewords, where information positions associated with an indeterminate or unassigned logic state are assigned with a respective assumed logic state, which may extend a capability of error detection or error correction compared to handling errors with unknown positions.

公开(公告)号：US20220199129A1

公开(公告)日：2022-06-23

申请号：US17550535

申请日：2021-12-14

Applicant: Micron Technology, Inc.

Inventor： Angelo Visconti ,  Daniele Balluchi ,  Giorgio Servalli

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/22

Abstract: Systems, apparatuses, and methods related to memory activation timing management are described herein. In an examples, memory activation timing management can include receiving a first command associated with a set of memory cells, activating the set of memory cells to perform a memory access responsive to the first command, pre-charging the set of memory cells associated with the first command, receiving a second command associated with the set of memory cells, determining that the set of memory cells associated with the first command is a recently activated set of the plurality of sets of memory cells, imparting a delay, and applying a sensing voltage to the set of memory cells associated with the second command to perform a memory access responsive to the second command.

公开(公告)号：US11348635B2

公开(公告)日：2022-05-31

申请号：US16834941

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Andrea Locatelli ,  Giorgio Servalli ,  Angelo Visconti

IPC: G11C11/4096 ,  G11C11/22 ,  G11C11/4097 ,  G11C11/406 ,  G11C11/4091

Abstract: Methods, systems, and devices for biasing a memory cell during a read operation are described. For example, a memory device may bias a memory cell to a first voltage (e.g., a read voltage) during an activation phase of a read operation. After biasing the memory cell to the first voltage, the memory device may bias the memory cell to a second voltage greater than the first voltage (e.g., a write voltage) during the activation phase of the read operation. After biasing the memory cell to the second voltage, the memory device may initiate a refresh phase of the read operation. Based on a value stored by the memory cell prior to biasing the memory cell to the first voltage, the memory device may initiate a precharge phase of the read operation.