公开(公告)号：US20070061634A1

公开(公告)日：2007-03-15

申请号：US11227831

申请日：2005-09-15

Applicant: Suresh Marisetty ,  Andrew Fish ,  Koichi Yamada ,  Scott Brenden ,  James Crossland ,  Shivnandan Kaushik ,  Mohan Kumar ,  Jose Vargas

Inventor： Suresh Marisetty ,  Andrew Fish ,  Koichi Yamada ,  Scott Brenden ,  James Crossland ,  Shivnandan Kaushik ,  Mohan Kumar ,  Jose Vargas

IPC: G06F11/00

CPC classification number: G06F11/0793 ,  G06F11/0706

Abstract: Methods and architectures for performing hardware error handling using coordinated operating system (OS) and firmware services. In one aspect, a firmware interface is provided to enable an OS to access firmware error-handling services. Such services enable the OS to access error data concerning platform hardware errors that may not be directed accessed via a platform processor or through other conventional approaches. Techniques are also disclosed for intercepting the processing of hardware error events and directing control to firmware error-handling services prior to attempting to service the error using OS-based services. The firmware services may correct hardware errors and/or log error data that may be later accessed by the OS or provided to a remote management server using an out-of-band communication channel. In accordance with another aspect, the firmware intercept and services may be performed in a manner that is transparent to the OS.

Abstract translation: 使用协调操作系统（OS）和固件服务执行硬件错误处理的方法和架构。 在一个方面，提供固件接口以使OS能够访问固件错误处理服务。 这样的服务使得OS能够访问有关平台硬件错误的错误数据，这些错误数据可能不会通过平台处理器或其他常规方法被定向访问。 还公开了用于在使用基于OS的服务尝试服务错误之前拦截硬件错误事件的处理以及将控制引导到固件错误处理服务的技术。 固件服务可以纠正OS稍后访问或使用带外通信信道提供给远程管理服务器的硬件错误和/或日志错误数据。 根据另一方面，固件拦截和服务可以以对OS是透明的方式来执行。

公开(公告)号：US20070011536A1

公开(公告)日：2007-01-11

申请号：US11157526

申请日：2005-06-21

Applicant: Rahul Khanna ,  Mohan Kumar ,  Jay Nejedlo

Inventor： Rahul Khanna ,  Mohan Kumar ,  Jay Nejedlo

IPC: G01R31/28

CPC classification number: G06F11/27

Abstract: Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is posted, wherein the link status is based at least in part on the result from the link training and the result from the BIST.

Abstract translation: 执行链接的训练，其中链路是计算机系统的两个设备之间的互连。 链接的内置自检（BIST）被执行。 将链接训练的结果与BIST的结果进行比较。 张贴链接的链接状态，其中链接状态至少部分地基于链接训练的结果和来自BIST的结果。

公开(公告)号：US20050144434A1

公开(公告)日：2005-06-30

申请号：US10751250

申请日：2003-12-31

Applicant: Billy Taylor ,  Mohan Kumar ,  Wilson Smoak ,  David O'Shea ,  Bassam Coury ,  Priscilla Lam ,  Tom Slaight

Inventor： Billy Taylor ,  Mohan Kumar ,  Wilson Smoak ,  David O'Shea ,  Bassam Coury ,  Priscilla Lam ,  Tom Slaight

IPC: G06F1/24 ,  G06F9/455 ,  G06F15/177

CPC classification number: G06F15/177 ,  G06F1/24 ,  G06F9/45533

Abstract: A system that may optionally be partitioned into multiple domains is disclosed. Each domain is capable of independently powering on, executing a firmware program, and loading an operating system, including a legacy operating system, as well as running an application program that is distinct from programs running on another domain. Interrupts, including boot interrupts, reset handlers, and inter-chassis communications are initialized differently, depending on whether the system is to be partitioned or not. The cost of redundant hardware and/or firmware is substantially avoided, yet the system fully supports multiple domains.

Abstract translation: 公开了可选地被划分成多个域的系统。 每个域都能够独立地加电，执行固件程序，以及加载包括旧版操作系统在内的操作系统，以及运行与在其他域上运行的程序不同的应用程序。 中断，包括引导中断，复位处理程序和机架间通信根据系统是否要进行分区，进行不同的初始化。 基本上避免了冗余硬件和/或固件的成本，但是系统完全支持多个域。

公开(公告)号：US09779094B2

公开(公告)日：2017-10-03

申请号：US13406398

申请日：2012-02-27

Applicant: Mohan Kumar ,  Gary Lehrman ,  Hari Krishna Dara

Inventor： Mohan Kumar ,  Gary Lehrman ,  Hari Krishna Dara

IPC: G06F7/00 ,  G06F17/30

CPC classification number: G06F17/30038 ,  G06F17/30873

Abstract: The invention provides for techniques to process and produce email documents. The techniques provide for organizing a first plurality of email documents into a plurality of document groups, reviewing a document group from the plurality of document groups, and associating a review content with the document group. The techniques provide for ways to propagate the review content to one or more email documents associated with the document group and producing a second plurality of email documents. The techniques provide for annotating one or more email documents in accordance with the review content. Depending on the embodiment, review content may include text, graphics, audio, tag, and multimedia information. Produced documents can be searched and browsed in accordance with information in the review content. Email documents can be grouped by information in meta information and/or header information associated with the email documents into various groups, including threads or conversations, for example.

公开(公告)号：US09430372B2

公开(公告)日：2016-08-30

申请号：US13997940

申请日：2011-09-30

Applicant: Murugasamy K. Nachimuthu ,  Mohan Kumar

Inventor： Murugasamy K. Nachimuthu ,  Mohan Kumar

IPC: G06F12/00 ,  G06F12/02 ,  G06F9/44 ,  G06F13/14 ,  G06F12/08 ,  G11C13/00

CPC classification number: G06F12/0868 ,  G06F9/4401 ,  G06F9/4403 ,  G06F12/00 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0866 ,  G06F13/14 ,  G06F2212/1041 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/608 ,  G11C13/0004 ,  Y02D10/13

Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in the platform storage hierarchy. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM is coupled to the processor to be directly accessed by the processor without going through an I/O subsystem. The NVRAM stores a Basic Input and Output System (BIOS). During a Pre-Extensible Firmware Interface (PEI) phase of the boot process, the cache within the processor can be used in a write-back mode for execution of the BIOS.

Abstract translation: 在计算机系统中使用非易失性随机存取存储器（NVRAM）来在平台存储层级中执行多个角色。 NVRAM是字节可重写的，可由处理器字节擦除。 NVRAM被耦合到处理器以由处理器直接访问，而不经过I / O子系统。 NVRAM存储基本输入和输出系统（BIOS）。 在引导过程的预扩展固件接口（PEI）阶段期间，处理器内的缓存可以用于执行BIOS的回写模式。

公开(公告)号：US20140059368A1

公开(公告)日：2014-02-27

申请号：US13977635

申请日：2012-11-21

Applicant: Neelam Chandwani ,  Mohan Kumar ,  Sarathy Jayakumar

Inventor： Mohan Kumar ,  Sarathy Jayakumar ,  Neelam Chandwani

IPC: G06F1/32

CPC classification number: G06F9/4403 ,  G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/22 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/384 ,  G06F9/44 ,  G06F9/4401 ,  G06F9/4418 ,  G06F9/445 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3447 ,  G06F11/3466 ,  G06F11/3664 ,  G06F11/3672 ,  G06F11/3688 ,  G06F15/7871 ,  G06F17/30339 ,  G06F2209/501 ,  G06F2217/78 ,  Y02D10/126 ,  Y02D10/172

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

Abstract translation: 在一些实施例中，只要平台硬件符合PPM接口，PPM接口可以被提供有功能，以便于一个或多个存储器节点的OS存储器功率状态管理，而不管特定的平台硬件配置。

公开(公告)号：US20140053024A1

公开(公告)日：2014-02-20

申请号：US13977625

申请日：2012-11-21

Applicant: Sarathy Jayakumar ,  Jose Andy Vargas ,  Mohan Kumar

Inventor： Mohan Kumar ,  Sarathy Jayakumar ,  Jose Andy Vargas

IPC: G06F11/36

CPC classification number: G06F9/4403 ,  G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/22 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/384 ,  G06F9/44 ,  G06F9/4401 ,  G06F9/4418 ,  G06F9/445 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3447 ,  G06F11/3466 ,  G06F11/3664 ,  G06F11/3672 ,  G06F11/3688 ,  G06F15/7871 ,  G06F17/30339 ,  G06F2209/501 ,  G06F2217/78 ,  Y02D10/126 ,  Y02D10/172

Abstract: In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, hardware component error injection.

Abstract translation: 在一些实施例中，可以提供用于计算平台的PPM接口，其具有通过PPM接口向OS提供硬件组件错误注入的功能。

公开(公告)号：US08615232B2

公开(公告)日：2013-12-24

申请号：US13556297

申请日：2012-07-24

Applicant: Gandarvakottai V. Kumar ,  Harish Amilineni ,  Mohan Kumar ,  Prakash K. Senapati

Inventor： Gandarvakottai V. Kumar ,  Harish Amilineni ,  Mohan Kumar ,  Prakash K. Senapati

IPC: H04W4/00 ,  H04W36/00

CPC classification number: H04W8/04 ,  H04W4/90 ,  H04W8/06 ,  H04W8/12

Abstract: Systems and methods of mobile communication roaming where a subscriber's home network and a roaming network used by the subscriber do not have a roaming agreement. Roaming between an alliance of coordinated operators having bilateral roaming relationships and operators who do not have roaming agreements with the alliance is provided. By subscribing to the system, a non-alliance operator can gain roaming access to alliance networks having existing bilateral roaming relationships. An authentication message is received from a roaming network in which a subscriber is roaming and the message is authenticated if there is a roaming relationship. The authentication message is forwarded to the home network via an alliance network and responsive to the indication that the authentication message was received at a roaming network, roaming transactions are enabled for the subscriber within the roaming network.

Abstract translation: 移动通信漫游的系统和方法，其中订户的家庭网络和用户使用的漫游网络不具有漫游协议。 提供了具有双边漫游关系的协调运营商联盟与没有与联盟的漫游协议的运营商之间的漫游。 通过订阅系统，非联盟运营商可以获得具有现有双边漫游关系的联盟网络的漫游访问。 从漫游网络接收认证消息，其中订户正在漫游，并且如果存在漫游关系，则该消息被认证。 认证消息经由联盟网络转发到家庭网络，并且响应于在漫游网络中接收到认证消息的指示，漫游网络内的用户可以进行漫游交易。

公开(公告)号：US20120046010A1

公开(公告)日：2012-02-23

申请号：US13214738

申请日：2011-08-22

Applicant: G. V. Kumar ,  Harish Amilineni ,  Mohan Kumar ,  Prakash K. Senapati

Inventor： G. V. Kumar ,  Harish Amilineni ,  Mohan Kumar ,  Prakash K. Senapati

IPC: H04W4/26 ,  H04W8/04

CPC classification number: H04W8/04 ,  H04W4/90 ,  H04W8/06 ,  H04W8/12

Abstract: A system and method of mobile communication roaming where a subscriber's home network and a roaming network used by the subscriber do not have a roaming agreement. The roaming network sends a “Send Authentication/Parameters” request to the home network via an intelligent roaming system on or attached to the backbone. The home network sends an authentication response to the “Send Authentication/Parameters” request from the home network to the roaming network via the backbone and intelligent roaming system. The roaming network sends a “Update Location” request from the roaming network to the intelligent roaming system. The visitor locator register (VLR) address in the “Update Location” request is replaced with the VLR address of the intelligent roaming system to create a modified update request. The modified update request is sent from the intelligent roaming system to the home network. The home network sends an update response to the modified update request to the roaming network via the backbone and intelligent roaming system.

Abstract translation: 移动通信漫游的系统和方法，其中订户的家庭网络和用户使用的漫游网络不具有漫游协议。 漫游网络通过智能漫游系统向主网络发送“发送认证/参数”请求，该智能漫游系统在骨干网上或连接到骨干网。 家庭网络通过骨干网和智能漫游系统向家庭网络向漫游网络发送“发送认证/参数”请求的认证响应。 漫游网络从漫游网络向智能漫游系统发送“更新位置”请求。 “更新位置”请求中的访问者定位器寄存器（VLR）地址被智能漫游系统的VLR地址替换，以创建修改的更新请求。 修改的更新请求从智能漫游系统发送到家庭网络。 家庭网络通过骨干网和智能漫游系统向漫游网络发送对修改的更新请求的更新响应。

公开(公告)号：US07725637B2

公开(公告)日：2010-05-25

申请号：US11967299

申请日：2007-12-31

Applicant: Mohan Kumar ,  Sarathy Jayakumar ,  Sham M Datta

Inventor： Mohan Kumar ,  Sarathy Jayakumar ,  Sham M Datta

IPC: G06F13/24

CPC classification number: G06F9/4812

Abstract: A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses. The method further includes directing each system management interrupt interprocessor interrupt to the corresponding processor. An associated machine readable medium is also disclosed.

Abstract translation: 一种方法包括确定多个存储器地址，每个存储器地址彼此不同。 该方法还包括产生多个系统管理中断处理器中断，每个系统管理中断处理器中断在系统中的多个处理器中具有对应的处理器，并且每个系统管理中断处理器中断包括多个存储器地址之一。 该方法还包括将每个系统管理中断处理器中断引导到相应的处理器。 还公开了一种相关的机器可读介质。