LOW OXYGEN CONTENT SEMICONDUCTOR MATERIAL FOR SURFACE ENHANCED PHOTONIC DEVICES AND ASSOCIATED METHODS
    41.
    发明申请
    LOW OXYGEN CONTENT SEMICONDUCTOR MATERIAL FOR SURFACE ENHANCED PHOTONIC DEVICES AND ASSOCIATED METHODS 审中-公开
    表面增强光电器件的低氧含量半导体材料及相关方法

    公开(公告)号:US20110121424A1

    公开(公告)日:2011-05-26

    申请号:US12771848

    申请日:2010-04-30

    IPC分类号: H01L31/105 H01L21/22

    摘要: Radiation-absorbing semiconductor devices and associated methods of making and using are provided. In one aspect, for example, a method for making a radiation-absorbing semiconductor device having enhanced photoresponse can include forming an active region on a surface of a low oxygen content semiconductor, and annealing the low oxygen content semiconductor to a temperature of from about 300° C. to about 1100° C., wherein the forming of the active region and the annealing of the low oxygen content semiconductor are performed in a substantially oxygen-depleted environment.

    摘要翻译: 提供了辐射吸收半导体器件及相关的制造和使用方法。 在一个方面,例如,用于制造具有增强的光响应的辐射吸收半导体器件的方法可以包括在低氧含量半导体的表面上形成有源区,并将低氧含量半导体退火至约300 约1100℃,其中活性区的形成和低氧含量半导体的退火在基本上耗氧的环境中进行。

    Magnetic Tunnel Junction Device and Fabrication
    42.
    发明申请
    Magnetic Tunnel Junction Device and Fabrication 有权
    磁隧道结设备及制造

    公开(公告)号:US20110049656A1

    公开(公告)日:2011-03-03

    申请号:US12557611

    申请日:2009-09-11

    申请人: Xia Li Seung H. Kang

    发明人: Xia Li Seung H. Kang

    摘要: A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming a top electrode layer over an MTJ structure. The top electrode layer includes a first nitrified metal.

    摘要翻译: 公开了一种磁性隧道结(MTJ)器件及其制造方法。 在特定实施例中,形成磁性隧道结(MTJ)器件的方法包括在MTJ结构上形成顶部电极层。 顶部电极层包括第一硝化金属。

    Magnetic Element With Storage Layer Materials
    44.
    发明申请
    Magnetic Element With Storage Layer Materials 有权
    磁性元素与存储层材料

    公开(公告)号:US20100176471A1

    公开(公告)日:2010-07-15

    申请号:US12352648

    申请日:2009-01-13

    IPC分类号: H01L29/82 H01L21/00

    摘要: According to an embodiment of the invention, a magnetic tunnel junction (MTJ) element includes a reference ferromagnetic layer, a storage ferromagnetic layer, and an insulating layer. The storage ferromagnetic layer includes a CoFeB sub-layer coupled to a CoFe sub-layer and/or a NiFe sub-layer through a non-magnetic sub-layer. The insulating layer is disposed between the reference and storage ferromagnetic layers.

    摘要翻译: 根据本发明的实施例,磁性隧道结(MTJ)元件包括参考铁磁层,存储铁磁层和绝缘层。 存储铁磁层包括通过非磁性子层耦合到CoFe子层和/或NiFe子层的CoFeB子层。 绝缘层设置在参考和存储铁磁层之间。

    Taste Receptors of the T1r Family from Domestic Dog
    45.
    发明申请
    Taste Receptors of the T1r Family from Domestic Dog 有权
    来自家庭狗的T1r家庭的滋味受体

    公开(公告)号:US20070287154A1

    公开(公告)日:2007-12-13

    申请号:US11578472

    申请日:2005-04-14

    摘要: The present invention relates to the discovery of several genes of the domestic dog (Canine familiaris) associated with taste perception. The invention provides, inter alia, the nucleotide sequence of the canine Tas1r1, Tas1r2, and Tas1r3 receptor genes, the amino acid sequences of the polypeptides encoded thereby, and antibodies to the polypeptides. The present invention also relates to methods for screening for compounds that modify the genes' function or activity, the compounds identified by such screens, and mimetics of the identified compounds. The invention further provides methods for modifying the taste preferences, ingestive responses, or general behavior of a mammal such as a dog by administering compounds that affect the function or activity of the gene or the polypeptide encoded thereby.

    摘要翻译: 本发明涉及与味觉相关的家犬(Canine familiaris)的几种基因的发现。 本发明特别提供了犬Tas1r1,Tas1r2和Tas1r3受体基因的核苷酸序列,由此编码的多肽的氨基酸序列以及针对多肽的抗体。 本发明还涉及用于筛选修饰基因的功能或活性的化合物的方法,由这种筛选鉴定的化合物以及鉴定的化合物的模拟物。 本发明还提供了通过施用影响基因的功能或活性的化合物或由其编码的多肽来修饰哺乳动物(例如狗)的味道偏好,摄入反应或一般行为的方法。

    Method and system to reduce switching signal noise on a device and a device as result thereof
    46.
    发明授权
    Method and system to reduce switching signal noise on a device and a device as result thereof 有权
    降低设备和设备上开关信号噪声的方法和系统

    公开(公告)号:US06521486B1

    公开(公告)日:2003-02-18

    申请号:US09645923

    申请日:2000-08-24

    IPC分类号: H01L2144

    摘要: A method, and system for reducing switching noise on a device, and an improved capacitor-integrated device is disclosed. At least one conductive line is deposited within a device. Additionally, at least one capacitor is attached to the at least one conductive line. Once the capacitor is attached to the conductive line, an improved capacitor-integrated circuit device results. The method and system of the present invention provides for the addition of at least one capacitor to be added between the power supply pins on at least one IC device. By doing so, switching signal noise is reduced. As a result of the method and system of the present invention, the resulting improved device can be efficiently used to check various qualities such as the level of ground bouncing noise, or switching signal noise reduction, without changing the circuit design of the device.

    摘要翻译: 公开了一种用于降低器件上的开关噪声的方法和系统,以及改进的电容器集成器件。 至少一条导线被放置在器件内。 另外,至少一个电容器连接到至少一个导电线。 一旦电容器连接到导线上,就会产生改进的电容集成电路器件。 本发明的方法和系统提供了在至少一个IC器件上添加至少一个要添加在电源引脚之间的电容器。 通过这样做,减少了开关信号噪声。 作为本发明的方法和系统的结果,不改变设备的电路设计,可以有效地利用所得到的改进的装置来检查诸如地面跳动噪声的电平或切换信号噪声降低的各种特性。

    Method of patterning gate electrodes with high K gate dielectrics
    48.
    发明授权
    Method of patterning gate electrodes with high K gate dielectrics 有权
    用高K栅极电介质构图栅电极的方法

    公开(公告)号:US06306741B1

    公开(公告)日:2001-10-23

    申请号:US09615809

    申请日:2000-07-13

    IPC分类号: H01L213205

    摘要: A buffer layer and a gate dielectric layer overlying a substrate having at least one active area is provided. A sacrificial oxide layer is formed over the gate dielectric layer. A nitride layer is formed over the sacrificial oxide layer. The nitride layer is patterned to form an opening therein within the active area exposing a portion of the sacrificial oxide layer within the opening. The portion of the sacrificial oxide layer within the opening is stripped, exposing a portion of the underlying gate dielectric layer within the opening. A gate electrode is formed within opening over the portion of the gate dielectric layer. The remaining nitride layer is selectively removed. The remaining sacrificial oxide layer is then stripped and removed.

    摘要翻译: 提供了具有至少一个有效区域的衬底上的缓冲层和栅介质层。 牺牲氧化物层形成在栅极介电层上。 在牺牲氧化物层上形成氮化物层。 图案化氮化物层以在有效区域内形成开口,露出开口内部的牺牲氧化物层的一部分。 剥离开口内的牺牲氧化物层的部分,将下面的栅极介电层的一部分暴露在开口内。 栅极电极形成在栅极电介质层的部分的开口内。 剩余的氮化物层被选择性地去除。 然后剥离并除去剩余的牺牲氧化物层。

    Method for bringing up lower level metal nodes of multi-layered integrated circuits for signal acquisition
    49.
    发明授权
    Method for bringing up lower level metal nodes of multi-layered integrated circuits for signal acquisition 失效
    提高用于信号采集的多层集成电路的下级金属节点的方法

    公开(公告)号:US06171944B2

    公开(公告)日:2001-01-09

    申请号:US09074627

    申请日:1998-05-07

    IPC分类号: H01L214763

    摘要: A method for bringing up lower level metal nodes of multi-layered IC devices (200) includes a step of boring a passage (210) down through the obstructing or non-target metal layers (220) exposing these layers, through the Inter Layer Dielectric layers (230), stopping at the target metal layer (240), and a step of depositing Gallium implanted insulator (250, 260) forming a node structure (280) with a conductive core (250) and an insulative sheath (260). The conductive core (250) brings up the target metal node or layer (240) and the insulative sheath (260) isolates the exposed non-target metal nodes or layers (220) from the target metal node (240) and the conductive core (250).

    摘要翻译: 一种用于提升多层IC器件(200)的下层金属节点的方法包括将通道(210)向下穿过暴露这些层的阻挡或非目标金属层(220)穿过层间介质 在所述目标金属层(240)处停止的层(230),以及形成具有导电芯(250)和绝缘护套(260)的形成节点结构(280)的镓注入绝缘体(250,260)的步骤。 导电芯(250)引出目标金属节点或层(240),并且绝缘护套(260)将暴露的非目标金属节点或层(220)与目标金属节点(240)和导电芯 250)。

    Backside exposure of desired nodes in a multi-layer integrated circuit
    50.
    发明授权
    Backside exposure of desired nodes in a multi-layer integrated circuit 失效
    多层集成电路中所需节点的背面曝光

    公开(公告)号:US6147399A

    公开(公告)日:2000-11-14

    申请号:US148666

    申请日:1998-09-04

    申请人: Xia Li Daniel Yim

    发明人: Xia Li Daniel Yim

    IPC分类号: H01L23/525 H01L23/053

    CPC分类号: H01L23/525 H01L2924/0002

    摘要: Aspects for exposing local areas for desired nodes in a multi-layer integrated circuit from the backside are described. In an exemplary method aspect, the method includes removing a predetermined portion of a first backside layer, opening chosen local areas with focused ion beam etching through at least the first backside layer, and exposing a desired node in a metal layer lower than the first backside layer with reactive ion etching. The method further includes removing the predetermined portion by performing reactive ion etching to a predetermined stop point. Alternatively, the first backside layer is mechanically polished to a predetermined thickness. Additionally, the method includes utilizing a high current ion beam during the focused ion beam etching.

    摘要翻译: 描述了用于从背面暴露多层集成电路中的期望节点的局部区域的方面。 在示例性方法方面,该方法包括去除第一背面层的预定部分,通过至少第一背面层的聚焦离子束蚀刻来打开所选择的局部区域,以及在低于第一背面层的金属层中暴露期望的节点 层与反应离子蚀刻。 该方法还包括通过对预定的停止点进行反应离子蚀刻来去除预定部分。 或者,将第一背面层机械抛光至预定厚度。 此外,该方法包括在聚焦离子束蚀刻期间利用高电流离子束。