公开(公告)号：US08658497B2

公开(公告)日：2014-02-25

申请号：US13343331

申请日：2012-01-04

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/336

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over a high-k dielectric as is metal logic gate of a logic transistor. The logic transistor is formed, including forming source/drains, while the metal select gate of the NVM cell is formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using metal nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.

摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 NVM单元的金属选择栅极形成在高k电介质上，如逻辑晶体管的金属逻辑门。 在形成NVM单元的金属选择栅极的同时形成逻辑晶体管，包括形成源极/漏极。 逻辑晶体管被保护，同时形成NVM单元，包括在金属选择栅极的一部分和衬底上的电荷存储区域的一部分上使用金属纳米晶体和金属控制栅极形成电荷存储区域。 蚀刻电荷存储区域以与金属控制栅极对准。

公开(公告)号：US20140001432A1

公开(公告)日：2014-01-02

申请号：US13539070

申请日：2012-06-29

申请人： Mark D. Hall ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Mehul D. Shroff

IPC分类号： H01L21/02 ,  H01L29/66 ,  B82Y40/00

CPC分类号： H01L29/0676 ,  B60C23/00 ,  B81B1/00 ,  B81B2203/0361 ,  B82Y20/00 ,  B82Y30/00 ,  B82Y40/00 ,  G01L9/06 ,  G01N33/0031 ,  G02B6/107 ,  G02B6/126 ,  G02B2006/12097 ,  H01L21/3086 ,  H01L29/0665 ,  H01L29/66 ,  H01L33/18 ,  H01L41/1132 ,  H01L43/02

摘要： A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.

摘要翻译： 公开的制造混合纳米柱装置的方法包括在基底上形成掩模和硬掩模上的纳米团簇层。 然后蚀刻硬掩模以将由第一层纳米团簇形成的图案转移到硬掩模的第一区域中。 在基板上形成第二纳米团簇层。 蚀刻覆盖衬底的第二区域的硬掩模的第二区域，以在硬掩模中产生第二图案。 然后将衬底通过硬掩模蚀刻以在衬底的第一区域中形成第一组纳米柱，并在衬底的第二区域中形成第二组纳米柱。 通过改变第一和第二层纳米团簇之间的纳米团簇沉积步骤，第一组和第二组纳米颗粒将呈现不同的特征。

公开(公告)号：US20130330893A1

公开(公告)日：2013-12-12

申请号：US13491771

申请日：2012-06-08

申请人： Mark D. Hall ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Mehul D. Shroff

IPC分类号： H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11534 ,  H01L27/11539 ,  H01L27/11573 ,  H01L29/66545 ,  H01L29/66833

摘要： A first dielectric layer is formed in an NVM region and a logic region. A charge storage layer is formed over the first dielectric layer and is patterned to form a dummy gate in the logic region and a charge storage structure in the NVM region. A second dielectric layer is formed in the NVM and logic regions which surrounds the charge storage structure and dummy gate. The second dielectric layer is removed from the NVM region while protecting the second dielectric layer in the logic region. The dummy gate is removed, resulting in an opening. A third dielectric layer is formed over the charge storage structure and within the opening, and a gate layer is formed over the third dielectric layer and within the opening, wherein the gate layer forms a control gate layer in the NVM region and the gate layer within the opening forms a logic gate.

摘要翻译： 在NVM区域和逻辑区域中形成第一介电层。 电荷存储层形成在第一电介质层之上，并被图案化以在逻辑区域中形成伪栅极，并在NVM区域中形成电荷存储结构。 在NVM和围绕电荷存储结构和虚拟栅极的逻辑区域中形成第二介质层。 从NVM区域去除第二介电层，同时保护逻辑区域中的第二介质层。 去除虚拟门，导致开口。 在电荷存储结构之上和开口内形成第三电介质层，并且栅极层形成在第三介电层之上和开口内，其中栅极层在NVM区域内形成控制栅极层，在栅极层内形成栅极层 开幕式构成逻辑门。

公开(公告)号：US08574987B1

公开(公告)日：2013-11-05

申请号：US13491760

申请日：2012-06-08

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/823456 ,  H01L27/11534 ,  H01L29/66545

摘要： A first dielectric layer is formed over a semiconductor layer in an NVM region and a logic region. A charge storage layer is formed over the first dielectric layer in the NVM and logic regions. The charge storage layer is patterned to form a dummy gate in the logic region and a charge storage structure in the NVM region. A second dielectric layer is formed over the semiconductor layer in the NVM and logic regions which surrounds the charge storage structure and the dummy gate. The dummy gate is replaced with a logic gate. The second dielectric layer is removed from the NVM region while protecting the second dielectric layer in the logic region. A third dielectric layer is formed over the charge storage structure, and a control gate layer is formed over the third dielectric layer.

摘要翻译： 在NVM区域和逻辑区域中的半导体层上形成第一介电层。 在NVM和逻辑区域中的第一介电层上形成电荷存储层。 对电荷存储层进行图案化以在逻辑区域中形成伪栅极，并在NVM区域中形成电荷存储结构。 在NVM的半导体层上形成第二电介质层，围绕电荷存储结构和虚拟栅极的逻辑区域形成。 虚拟门被一个逻辑门代替。 从NVM区域去除第二介电层，同时保护逻辑区域中的第二介质层。 在电荷存储结构上形成第三电介质层，并且在第三介电层上形成控制栅层。

公开(公告)号：US20130267072A1

公开(公告)日：2013-10-10

申请号：US13780591

申请日：2013-02-28

申请人： Mark D. Hall ,  Frank K. Baker, JR. ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Frank K. Baker, JR. ,  Mehul D. Shroff

IPC分类号： H01L21/82

CPC分类号： H01L21/82 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/7881

摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region.

摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 在NVM区域中，在第一热生长含氧层上形成NVM单元的多晶硅选择栅极，在逻辑区域中，在高k电介质和多晶硅上形成功函数设定材料 在工作功能设置材料上形成虚拟门。 在形成第一热生长含氧层之后形成源极/漏极，侧壁间隔物和逻辑晶体管的硅化物区域。 多晶硅虚拟栅极由金属栅极代替。 在形成电荷存储区域的同时形成NVM单元时，保护逻辑晶体管。

公开(公告)号：US20130249015A1

公开(公告)日：2013-09-26

申请号：US13893026

申请日：2013-05-13

申请人： Gauri V. Karve ,  Mark D. Hall ,  Srikanth B. Samavedam

发明人： Gauri V. Karve ,  Mark D. Hall ,  Srikanth B. Samavedam

IPC分类号： H01L27/092

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054

摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.

公开(公告)号：US20130178027A1

公开(公告)日：2013-07-11

申请号：US13780574

申请日：2013-02-28

申请人： Mark D. Hall ,  Frank K. Baker, JR. ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Frank K. Baker, JR. ,  Mehul D. Shroff

IPC分类号： H01L29/66

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/7881

摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer in an NVM region and a polysilicon dummy gate is formed over a second thermally-grown oxygen-containing layer in a logic region. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first and second thermally-grown oxygen-containing layers are formed. The second thermally-grown oxygen-containing layer and the dummy gate are replaced by a metal gate and a high-k dielectric. The logic transistor is protected while the NVM cell is then formed including forming a charge storage layer.

摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 在NVM区域中的第一热生长含氧层上形成NVM单元的多晶硅选择栅极，并且在逻辑区域中的第二热生长含氧层上形成多晶硅虚拟栅极。 在形成第一和第二热生长含氧层之后形成源极/漏极，侧壁间隔物和逻辑晶体管的硅化物区域。 第二热生长含氧层和虚拟栅极被金属栅极和高k电介质代替。 保护逻辑晶体管，同时形成NVM单元，包括形成电荷存储层。

公开(公告)号：US08389365B2

公开(公告)日：2013-03-05

申请号：US13077501

申请日：2011-03-31

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/11536 ,  H01L29/66825

摘要： A method for forming an integrated circuit for a non-volatile memory cell transistor is disclosed that includes: forming a layer of discrete storage elements over a substrate in a first region of the substrate and in a second region of the substrate; forming a first layer of dielectric material over the layer of discrete storage elements in the first region and the second region; forming a first layer of barrier work function material over the first layer of dielectric material in the first region and the second region; and removing the first layer of barrier work function material from the second region, the first layer of dielectric material from the second region, and the layer of discrete storage elements from the second region. After the removing, a second layer of barrier work function material is formed over the substrate in the first region and the second region. The second layer of barrier work function material is removed from the first region. A first gate of a memory device is formed in the first region. The first gate includes a portion of the first layer of barrier work function material. The memory device includes a charge storage structure including a portion of the layer of discrete storage elements. A second gate of a transistor is formed in the second region, the second gate including a portion of the second layer of barrier work function material.

摘要翻译： 公开了一种用于形成用于非易失性存储单元晶体管的集成电路的方法，其包括：在所述衬底的第一区域和所述衬底的第二区域中的衬底上形成离散存储元件层; 在所述第一区域和所述第二区域中的离散存储元件层上形成第一介电材料层; 在所述第一区域和所述第二区域中的所述第一介电材料层上形成阻挡功函数材料的第一层; 以及从所述第二区域去除所述第一层屏障功能材料，从所述第二区域去除所述第一介电材料层，以及从所述第二区域移除所述离散存储元件层。 在去除之后，在第一区域和第二区域中的衬底上形成第二层屏障功能材料层。 从第一区域去除第二层屏障功能材料。 存储器件的第一栅极形成在第一区域中。 第一栅极包括第一层屏障功能材料的一部分。 存储器件包括电荷存储结构，其包括离散存储元件层的一部分。 晶体管的第二栅极形成在第二区域中，第二栅极包括第二层屏障功能材料的一部分。

公开(公告)号：US08318576B2

公开(公告)日：2012-11-27

申请号：US13092046

申请日：2011-04-21

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/20

CPC分类号： H01L29/945 ,  H01L27/0629 ,  H01L29/66181

摘要： A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer below a trench opening, a capacitor dielectric layer and a recessed top capacitor plate that is covered by an STI region and isolated from cross talk by a sidewall dielectric layer.

摘要翻译： 一种半导体工艺和装置提供集成在集成电路中的浅沟槽隔离电容器结构，并且包括形成在沟槽开口下方的衬底层中的底部电容器板，覆盖的电容器电介质层和凹陷顶部电容器板 通过STI区域并且通过侧壁电介质层与串扰隔离。

公开(公告)号：US08304331B2

公开(公告)日：2012-11-06

申请号：US12787101

申请日：2010-05-25

申请人： Mark D. Hall

发明人： Mark D. Hall

IPC分类号： H01L21/425

CPC分类号： H01L21/26586 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7889 ,  H01L29/7926

摘要： Angled ion implants are utilized to form doped regions in a semiconductor pillar formed in an opening of a mask. The pillar is formed to a height less than the height of the mask. Angled ion implantation can be used to form regions of a semiconductor device such as a body tie region, a halo region, or current terminal extension region of a semiconductor device implemented with the semiconductor pillar.

摘要翻译： 角度离子注入用于在形成在掩模开口中的半导体柱中形成掺杂区域。 支柱形成为小于面罩高度的高度。 角度离子注入可用于形成半导体器件的区域，例如半导体器件实体的半导体器件的主体连接区域，晕圈区域或电流端子延伸区域。