公开(公告)号：US06764212B1

公开(公告)日：2004-07-20

申请号：US09436637

申请日：1999-11-09

申请人： Takahisa Nitta ,  Nobuhiro Miki ,  Yoshiaki Yamaguchi

发明人： Takahisa Nitta ,  Nobuhiro Miki ,  Yoshiaki Yamaguchi

IPC分类号： B01F1504

CPC分类号： B01F15/042 ,  B01F5/0471 ,  B01F5/0475 ,  B01F15/0203 ,  B01F15/024 ,  B01F15/0244 ,  B01F2215/0096 ,  F04B43/0054 ,  F04B43/02 ,  F04B43/046 ,  F04F7/00 ,  F16K7/123 ,  G05D11/138 ,  H01L21/67051

摘要： A chemical supply system comprises, as principal elements, a chemical storage tank in which a liquid chemical for cleaning is stored in the state of its formulated concentrate, a chemical supply apparatus connected to the chemical storage tank for positively performing chemical supply, a piping system connected to the chemical supply apparatus to form a supply flow passage that is a passage for ultrapure water which the liquid chemical is to be mixed with, a pair of discharge nozzles disposed at end portions of the piping system so as to oppose surfaces of a wafer set in a cleaning chamber to supply a cleaning liquid onto the surfaces. Thereby, remarkable miniaturization/simplification of a cleaning liquid supply system including chemical tanks is intended, it is made possible easily and rapidly to compound and supply a cleaning liquid at an accurate chemical concentration, and particles or the like being generated and mixing in a cleaning liquid, are suppressed to the extremity.

摘要翻译： 作为主要要素的化学品供给系统包括：化学品储罐，其中用于清洗的液体化学品以其配制的浓缩物的状态储存;化学品供应装置，连接到化学品储存罐用于积极地进行化学品供应;管道系统 连接到化学物质供给装置，形成作为液体化学品混合的超纯水通道的供给流路，配置在管道系统的端部的一对排出喷嘴，以与晶片的表面相对 设置在清洁室中以将清洁液体供应到表面上。 因此，旨在使包含化学池的清洗液供给系统显着的小型化/简化，可以容易且快速地将化学浓度精确化合并提供清洗液，并在清洁中产生和混合 液体，被压制到肢体。

公开(公告)号：US06503464B1

公开(公告)日：2003-01-07

申请号：US09416415

申请日：1999-10-12

申请人： Nobuhiro Miki ,  Takahisa Nitta

发明人： Nobuhiro Miki ,  Takahisa Nitta

IPC分类号： B01J1908

CPC分类号： H01L21/67028 ,  A61L2/10 ,  A61L9/20 ,  B01J19/123 ,  C02F1/325 ,  C02F2103/04 ,  C02F2201/3228

摘要： An ultraviolet light reaction system is constructed for surface cleaning/surface processing, a processing speed and an apparatus size that can not be attained by any conventional chemical reaction system, are realized, and realization of a time-sharing performance/a high-throughput performance/a compact size is intended. Using an excimer ultraviolet lamp whose light source is excimer ultraviolet rays of a wavelength that transmissive distances to air, gas, and water are 2 mm or more, respectively, surface processing (such as a surface cleaning process) of a substrate disposed in a one-by-one substrate chamber is preformed.

摘要翻译： 构建用于表面清洁/表面处理的紫外光反应系统，通过任何常规化学反应系统不能实现的处理速度和设备尺寸，实现分时性能/高通量性能 /尺寸紧凑。 使用光源是对空气，气体和水的透射距离的波长的准分子紫外线的准分子紫外线灯分别为2mm以上的基板的表面处理（例如表面清洁处理） 一个基板室被预成型。

公开(公告)号：US4219369A

公开(公告)日：1980-08-26

申请号：US931007

申请日：1978-08-04

申请人： Katsumi Ogiue ,  Takahisa Nitta ,  Kazumichi Mitsusada ,  Masato Iwabuchi ,  Masanori Odaka

发明人： Katsumi Ogiue ,  Takahisa Nitta ,  Kazumichi Mitsusada ,  Masato Iwabuchi ,  Masanori Odaka

IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/32 ,  H01L21/388 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/26

CPC分类号： H01L21/388 ,  H01L21/033 ,  H01L21/308 ,  H01L21/32 ,  H01L21/7621 ,  H01L21/76216 ,  H01L21/76232 ,  H01L21/8222 ,  Y10S148/117 ,  Y10S148/143

摘要： The invention relates to a method of making a semiconductor integrated circuit device, and aims at diminishing the size of the isolating region which isolates the adjacent semiconductor elements from each other. The method of the invention has the steps of forming on a substrate a deposition layer of diffused impurities of different conductivity type from that of the substrate, forming a masking film having apertures on the deposition layer, effecting an etching through making use of the masking film as the diffusion mask, so as to etch the portions of the deposition layer and the substrate under the apertures, thereby to form grooves which divide the deposition layer into island-like deposition layer sections, and stretching and diffusing the impurities in each island-like deposition layer section to form a diffusion layer which constitutes a part of a semiconductor element.

摘要翻译： 本发明涉及一种制造半导体集成电路器件的方法，其目的在于减小将相邻半导体元件彼此隔离的隔离区的尺寸。 本发明的方法具有以下步骤：在衬底上形成不同导电类型的扩散杂质的沉积层与衬底的沉积层，在沉积层上形成具有孔的掩模膜，通过使用掩模膜进行蚀刻 作为扩散掩模，以蚀刻沉积层和基板下面的部分，从而形成将沉积层分成岛状沉积层部分的凹槽，并且将每个岛状沉积层中的杂质拉伸和扩散 沉积层部分以形成构成半导体元件的一部分的扩散层。

公开(公告)号：US5060045A

公开(公告)日：1991-10-22

申请号：US422640

申请日：1989-10-17

申请人： Nobuo Owada ,  Hiroyuki Akimori ,  Takahisa Nitta ,  Tohru Kobayashi ,  Shunji Sasabe ,  Mikinori Kawaji ,  Osamu Kasahara

发明人： Nobuo Owada ,  Hiroyuki Akimori ,  Takahisa Nitta ,  Tohru Kobayashi ,  Shunji Sasabe ,  Mikinori Kawaji ,  Osamu Kasahara

IPC分类号： H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L27/118

CPC分类号： H01L27/118

摘要： Disclosed is a semiconductor integrated circuit device adopting a gate array scheme, having a plurality of layers of wiring formed by a Design Automation system. The device according to the present invention includes a semiconductor substrate having basic cell forming regions, the basic cell forming regions being spaced from each other with wiring channel regions between adjacent basic cell forming regions. The wiring includes at least first-layer wiring lines arranged overlying the wiring channel regions; second-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions; and third-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions. The first-, second- and third-layer wiring lines respectively extend in first, second and third directions, the second direction being different from the first direction. The wiring pitches of the second-layer wiring lines and the third-layer wiring lines are set substantially equal to or smaller than the wiring pitch of th first-layer wiring lines. As a further aspect of the present invention, the ratio of wiring pitch of third-layer wiring lines to first-layer wiring lines can be 0.5, 1.0, 1.5 or 2.0. In addition, insulator films on which are formed the wiring lines are respectively subjected to flattening processes in order to flatten their upper surfaces, prior to providing the wiring lines thereon.

摘要翻译： 公开了一种采用门阵列方案的半导体集成电路装置，具有由设计自动化系统形成的多层布线。 根据本发明的器件包括具有碱性电池形成区域的半导体衬底，所述碱性电池形成区域彼此间隔开，并且在相邻的基本电池形成区域之间具有布线沟道区域。 布线至少包括布置在布线沟道区域上的第一层布线; 覆盖基本单元形成区域和布线沟道区域的第二层布线; 以及覆盖基本单元形成区域和布线沟道区域的第三层布线。 第一，第二和第三层布线分别在第一，第二和第三方向上延伸，第二方向不同于第一方向。 第二层布线和第三层布线的布线间距基本上等于或小于第一层布线的布线间距。 作为本发明的另一方面，第三层布线与第一层布线的布线间距的比可以为0.5,1.0,1.5或2.0。 此外，在其上形成布线的绝缘膜分别在其上提供布线之前分别进行平坦化处理以使其上表面变平。

公开(公告)号：US4111724A

公开(公告)日：1978-09-05

申请号：US750387

申请日：1976-12-14

申请人： Katumi Ogiue ,  Hiroyuki Kondo ,  Takashi Ishikawa ,  Takaaki Mori ,  Takahisa Nitta

发明人： Katumi Ogiue ,  Hiroyuki Kondo ,  Takashi Ishikawa ,  Takaaki Mori ,  Takahisa Nitta

IPC分类号： H01L21/331 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L23/485 ,  H01L29/73 ,  H01L21/306

CPC分类号： H01L23/485 ,  H01L21/743 ,  H01L21/76208 ,  H01L21/7621 ,  H01L2924/0002

摘要： In the production of a semiconductor integrated circuit device including a selective oxidation step at a high temperature using a nitride film as a mask for isolating respective element regions in a semiconductor wafer with oxidized regions, electrode contact regions and active regions are successively formed in each element region to be surrounded by the oxidized regions and thin oxide films are formed on exposed surfaces of the electrode contact regions, the thin semiconductor oxide films are removed simultaneously by immersed etching, and then electrode metal layers are formed thereon. The thickness of the oxide layer on which the electrode metal layers are formed is maintained almost uniform to ensure the isolation effect. Since a buried region in each element region is required only to make partial contact with the contact region at the bottom portion, the integration density of the elements in the integrated circuit can be increased.

公开(公告)号：US5105556A

公开(公告)日：1992-04-21

申请号：US230155

申请日：1988-08-09

申请人： Hideaki Kurokawa ,  Katsuya Ebara ,  Sankichi Takahashi ,  Harumi Matsuzaki ,  Hiroaki Yoda ,  Takahisa Nitta ,  Isao kouchi ,  Yukio Hishinuma

发明人： Hideaki Kurokawa ,  Katsuya Ebara ,  Sankichi Takahashi ,  Harumi Matsuzaki ,  Hiroaki Yoda ,  Takahisa Nitta ,  Isao kouchi ,  Yukio Hishinuma

IPC分类号： F26B3/00 ,  F26B7/00 ,  F26B21/14 ,  H01L21/00

CPC分类号： H01L21/67057 ,  F26B21/145 ,  F26B3/00 ,  F26B7/00

摘要： Vapor is separated from mist accompanying the vapor by passing the vapor through a porous membrane. The vapor having passed through the membrane is brought into contact with an object to be washed and condenses thereon, whereby the object is washed.

摘要翻译： 通过使蒸汽通过多孔膜，蒸气与伴随蒸气的雾分离。 使已经通过膜的蒸气与待洗涤物体接触并在其上冷凝，从而洗涤物体。

公开(公告)号：US4718539A

公开(公告)日：1988-01-12

申请号：US6249

申请日：1987-01-09

申请人： Ichiro Fukuwatari ,  Seiji Watanabe ,  Naoyuki Takahashi ,  Takahisa Nitta ,  Yoshio Saito

发明人： Ichiro Fukuwatari ,  Seiji Watanabe ,  Naoyuki Takahashi ,  Takahisa Nitta ,  Yoshio Saito

IPC分类号： B65G51/03 ,  B65G54/02 ,  H01L21/677 ,  B65G35/00

CPC分类号： H01L21/67784 ,  B65G51/03 ,  B65G54/02

摘要： A conveyor means for transporting precision parts is divided into a plurality of block units and compressed air is supplied selectively to each block unit where a transporting pallet is present so as to reduce consumption of compressed air to the minimum. Also, it ensures high carrying efficiency because of its slow starting and slow stopping without reducing the speed during running.

摘要翻译： 用于运输精密部件的传送装置被分成多个块单元，并且压缩空气被选择性地供给到存在传送托盘的每个块单元，以将压缩空气的消耗降低到最小。 此外，由于启动速度慢，停止运行缓慢，运行中不会降低速度，因此确保了高的承载效率。

公开(公告)号：USRE31506E

公开(公告)日：1984-01-24

申请号：US183100

申请日：1980-09-02

申请人： Katumi Ogiue ,  Hiroyuki Kondo ,  Takashi Ishikawa ,  Takaaki Mori ,  Takahisa Nitta

发明人： Katumi Ogiue ,  Hiroyuki Kondo ,  Takashi Ishikawa ,  Takaaki Mori ,  Takahisa Nitta

IPC分类号： H01L21/331 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L23/485 ,  H01L29/73

CPC分类号： H01L23/485 ,  H01L21/743 ,  H01L21/76208 ,  H01L21/7621 ,  H01L2924/0002

摘要： In the production of a semiconductor integrated circuit device including a selective oxidation step at a high temperature using a nitride film as a mask for isolating respective element regions in a semiconductor wafer with oxidized regions, electrode contact regions and active regions are successively formed in each element region to be surrounded by the oxidized regions and thin oxide films are formed on exposed surfaces of the electrode contact regions, the thin semiconductor oxide films are removed simultaneously by immersed etching, and then electrode metal layers are formed thereon. The thickness of the oxide layer on which the electrode metal layers are formed is maintained almost uniform to ensure the isolation effect. Since a buried region in each element region is required only to make partial contact with the contact region at the bottom portion, the integration density of the elements in the integrated circuit can be increased.

公开(公告)号：US4088516A

公开(公告)日：1978-05-09

申请号：US737032

申请日：1976-10-29

申请人： Hiroyuki Kondo ,  Takahisa Nitta ,  Yoshiro Moriguchi

发明人： Hiroyuki Kondo ,  Takahisa Nitta ,  Yoshiro Moriguchi

IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/32 ,  H01L21/762 ,  H01L29/732 ,  H01L21/22

CPC分类号： H01L21/32 ,  H01L21/316 ,  H01L21/7621 ,  H01L21/76216 ,  H01L29/732 ,  Y10S148/085

摘要： A method of manufacturing a semiconductor device, comprises the steps of masking desired parts of a semiconductor substrate with a material which is impervious to an etchant for the substrate, exposing the substrate to the etchant to thereby etch substrate parts which lie directly beneath end parts of the etchant-impervious material and substrate parts which are not masked, applying a solution preferentially into the parts directly beneath the end parts of the etchant-impervious material among the etched substrate parts, the solution being capable of being converted into a semiconduct or oxide by a predetermined heat treatment, and heat-treating the substrate in order to oxidize the etched substrate surface parts.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：用不透过衬底蚀刻剂的材料掩蔽半导体衬底的所需部分，将衬底暴露于蚀刻剂，从而蚀刻直接位于 不被掩蔽的不透光蚀刻材料和衬底部分，在蚀刻的衬底部分之间优先将溶液施加到蚀刻剂不渗透材料的端部正下方的部分中，该溶液能够通过以下方式转化为半导体或氧化物： 进行预定的热处理，并对基板进行热处理，以氧化蚀刻的基板表面部分。