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41.发明申请Dynamic random access memory (DRAM) capable of canceling out complimentary noise development in plate electrodes of memory cell capacitors 有权动态随机存取存储器（DRAM）能够消除存储单元电容器的平板电极中的互补噪声发展公开(公告)号：US20050270889A1
公开(公告)日：2005-12-08
申请号：US11198357
申请日：2005-08-08
申请人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
发明人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
IPC分类号： G11C11/401 , G11C5/02 , G11C5/06 , G11C7/02 , G11C7/18 , G11C8/00 , G11C11/34 , G11C11/4097 , H01L21/8242 , H01L27/02 , H01L27/108
CPC分类号： G11C7/02 , G11C5/025 , G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4097 , H01L27/0207 , H01L27/0214 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10897
摘要： Disclosed herein is a dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells provided on both sides with the sense amplifier array as the center are connected to one another while circuit connections in the sense amplifier array are being ensured by wiring means using the common electrodes.,
摘要翻译： 这里公开了一种动态RAM，其包括分别连接到多个动态存储单元的地址选择端的多个字线，分别连接到多个动态存储单元的输入/输出端并放置在多个动态存储单元中的多个互补位线对 方向相反，以及根据操作定时信号被提供有工作电压的读出放大器阵列，并且包括用于分别放大互补位线对之间的电压差的多个锁存电路。 在动态RAM中，以与感测放大器阵列为中心的两侧设置的多个动态存储单元的地址选择MOSFET和信息存储电容器之间的连接点对应的存储节点提供的公共电极彼此连接 而通过使用公共电极的布线装置来确保读出放大器阵列中的电路连接，
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公开(公告)号：US20050231787A1
公开(公告)日：2005-10-20
申请号：US10926053
申请日：2004-08-26
申请人： Osamu Tsuboi , Norinao Kouma , Hisao Okuda , Hiromitsu Soneda , Satoshi Ueda , Ippei Sawaki , Yoshitaka Nakamura
发明人： Osamu Tsuboi , Norinao Kouma , Hisao Okuda , Hiromitsu Soneda , Satoshi Ueda , Ippei Sawaki , Yoshitaka Nakamura
CPC分类号： G02B26/0841
摘要： A micro-oscillation element includes a frame, a movable functional part, a driving mechanism, a beam extending from the functional part to the driving mechanism, and a torsion connector for connecting the frame and the beam to each other. The connector defines a rotational axis about which the functional part rotates. The rotational axis crosses the longitudinal direction of the beam. The beam is shorter than the functional part in the longitudinal direction of the rotational axis.
摘要翻译： 微振荡元件包括框架，可动功能部件，驱动机构，从功能部件延伸到驱动机构的梁，以及用于将框架和梁彼此连接的扭转连接器。 连接器限定了功能部件绕其旋转的旋转轴线。 旋转轴线与梁的纵向方向交叉。 光束比旋转轴的纵向方向上的功能部分短。
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公开(公告)号：US20050037531A1
公开(公告)日：2005-02-17
申请号：US10791903
申请日：2004-03-04
申请人： Norinao Kouma , Osamu Tsuboi , Hisao Okuda , Hiromitsu Soneda , Mi Xiaoyu , Satoshi Ueda , Ippei Sawaki , Yoshitaka Nakamura
发明人： Norinao Kouma , Osamu Tsuboi , Hisao Okuda , Hiromitsu Soneda , Mi Xiaoyu , Satoshi Ueda , Ippei Sawaki , Yoshitaka Nakamura
CPC分类号： B81C1/00626 , B81B2201/0235 , B81B2201/042 , B81B2203/0136 , B81B2203/04
摘要： A method for manufacturing a micro-structural unit is provided. By the method, micro-machining is performed on a material substrate including first through third conductive layers and two insulating layers, one of which is interposed between the first and the second conductive layers, and the other between the second and the third conductive layers. The method includes several etching steps performed on the layers of the material substrate that are different in thickness.
摘要翻译： 提供一种微结构单元的制造方法。 通过该方法，在包括第一至第三导电层和两个绝缘层的材料基板上进行微加工，其中一个绝缘层介于第一和第二导电层之间，另一个位于第二和第三导电层之间。 该方法包括在不同厚度的材料基底的层上执行的几个蚀刻步骤。
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公开(公告)号：US20050030783A1
公开(公告)日：2005-02-10
申请号：US10938794
申请日：2004-09-13
申请人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
发明人： Tomonori Sekiguchi , Kazuhiko Kajigaya , Katsutaka Kimura , Riichiro Takemura , Tsugio Takahashi , Yoshitaka Nakamura
IPC分类号： G11C11/401 , G11C5/02 , G11C5/06 , G11C7/02 , G11C7/18 , G11C8/00 , G11C11/34 , G11C11/4097 , H01L21/8242 , H01L27/02 , H01L27/108 , G11C11/22
CPC分类号： G11C7/02 , G11C5/025 , G11C5/063 , G11C7/18 , G11C11/4074 , G11C11/4097 , H01L27/0207 , H01L27/0214 , H01L27/10814 , H01L27/10882 , H01L27/10885 , H01L27/10897
摘要： Disclosed herein is a dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells provided on both sides with the sense amplifier array as the center are connected to one another while circuit connections in the sense amplifier array are being ensured by wiring means using the common electrodes.
摘要翻译： 这里公开了一种动态RAM，其包括分别连接到多个动态存储单元的地址选择端的多个字线，分别连接到多个动态存储单元的输入/输出端并放置在多个动态存储单元中的多个互补位线对 方向相反，以及根据操作定时信号被提供有工作电压的读出放大器阵列，并且包括用于分别放大互补位线对之间的电压差的多个锁存电路。 在动态RAM中，以与感测放大器阵列为中心的两侧设置的多个动态存储单元的地址选择MOSFET和信息存储电容器之间的连接点对应的存储节点提供的公共电极彼此连接 而通过使用公共电极的布线装置来确保读出放大器阵列中的电路连接。
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45.发明授权Semiconductor integrated circuit device having spaced-apart electrodes and the method thereof 失效具有间隔开的电极的半导体集成电路装置及其方法公开(公告)号：US06756262B1
公开(公告)日：2004-06-29
申请号：US09708450
申请日：2000-11-09
申请人： Yoshitaka Nakamura , Isamu Asano , Satoru Yamada , Tsugio Takahashi , Yuzuru Ohji , Masayoshi Hirasawa , Takashi Yunogami , Tomonori Sekiguchi
发明人： Yoshitaka Nakamura , Isamu Asano , Satoru Yamada , Tsugio Takahashi , Yuzuru Ohji , Masayoshi Hirasawa , Takashi Yunogami , Tomonori Sekiguchi
IPC分类号： H01L218249
CPC分类号： H01L28/75 , H01L27/10814 , H01L27/10855 , H01L27/10894 , H01L28/55 , H01L28/65 , H01L28/90
摘要： Conduction reliability between a capacitor upper electrode and a plug connected to an upper layer wire is kept high to prevent connection defects and to reduce the resistance of the capacitor upper electrode. In a capacitor of a DRAM comprising a lower electrode 45 made of ruthenium, a capacitor insulating film 50 made of BST and an upper electrode 49, the upper electrode 49 has a laminate structure comprising a ruthenium film 47 formed on the side of the capacitor insulating film 50 and a tungsten film 48 formed over the former.
摘要翻译： 电容器上部电极和连接到上层电线的插头之间的传导可靠性保持较高，以防止连接缺陷并降低电容器上部电极的电阻。 在包括由钌制成的下电极45的电容器，由BST制成的电容器绝缘膜50和上电极49的情况下，上电极49具有包括形成在绝缘电容器侧的钌膜47的层叠结构 膜50和形成在前者上的钨膜48。
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46.发明授权公开(公告)号：US06664157B2
公开(公告)日：2003-12-16
申请号：US09775547
申请日：2001-02-05
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L27/10888 , H01L28/91
摘要： Plug electrodes of silicon are formed so as to be buried in through holes in a first insulating film, the plug electrodes being electrically connected to the source and drain regions of a MISFET on the main surface of a semiconductor substrate. Then, a second insulating film is deposited thereon and holes are formed therein such that the plug electrodes of silicon are exposed. A barrier film is formed on the surfaces of the silicon plugs, and in the holes a dielectric is formed to form lower electrodes of the capacitor elements and an upper electrode therefor.
摘要翻译： 形成硅的插入电极以埋在第一绝缘膜的通孔中，插塞电极与半导体衬底的主表面上的MISFET的源极和漏极区域电连接。 然后，在其上沉积第二绝缘膜，并在其中形成孔，使得硅的插塞电极露出。 在硅插头的表面上形成阻挡膜，并且在孔中形成电介质以形成电容器元件的下电极和用于其的上电极。
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公开(公告)号：US06521494B2
公开(公告)日：2003-02-18
申请号：US10211569
申请日：2002-08-05
申请人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
发明人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/28562 , H01L27/10814
摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film. The upper and lower electrodes and an oxide dielectric film together constitute capacitors of the memory cells.
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公开(公告)号：US06505866B1
公开(公告)日：2003-01-14
申请号：US09633852
申请日：2000-08-07
申请人： Yoshitaka Nakamura , Akihiro Tanaka , Tsutomu Uno , Osamu Igarashi , Noriyoshi Komiyama , Mitsuru Hirai
发明人： Yoshitaka Nakamura , Akihiro Tanaka , Tsutomu Uno , Osamu Igarashi , Noriyoshi Komiyama , Mitsuru Hirai
IPC分类号： F16L2500
CPC分类号： F16L37/0985
摘要： Provided is a highly reliable leak-proof pipe joint which is superior in workability, inexpensive and Light, superior in resistance against chlorine and oxygen contained in hot water or vapor, resistive against hydrolysis in hot water, superior in mechanical strength and impact resistance, and thereby capable of withstanding deformation due to water pressure or water hammer phenomenon. This pipe, joint has a main body and a connector or connecting the main body to a pipe, wherein at least either the main body or connector is formed from one type selected from a group consisting or resin in which thermoplastic elastomer is added to polyphenylene sulfide, polysulfone, polyphenyl sulfane, polyphthalimide and polyetherimide, and the main body and connector are formed integrally.
摘要翻译： 提供了一种高可靠性的防漏管接头，其加工性优良，价格低廉，耐热水或蒸汽中含有的氯和氧的耐受性优异，耐热水中的水解，机械强度和抗冲击性优异， 从而能够承受由于水压或水锤现象引起的变形。 该管接头具有主体和连接器或将主体连接到管道，其中主体或连接器中的至少一个由从热塑性弹性体加入到聚苯硫醚中的一种或多种树脂形成， ，聚砜，聚苯基砜，聚邻苯二甲酰亚胺和聚醚酰亚胺，并且主体和连接器一体地形成。
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49.发明授权公开(公告)号：US06503791B2
公开(公告)日：2003-01-07
申请号：US09767706
申请日：2001-01-24
申请人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
发明人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/28562 , H01L27/10814
摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film.
摘要翻译： 在包括多个存储单元的半导体器件中，在形成有多个孔的层间绝缘膜上形成防沉积膜，或者在层间绝缘膜和内表面上选择性地形成晶种膜， 孔的底面。 在发生底层依赖性的条件下，通过化学气相沉积在沉积防止膜上或通过利用种子膜在层间绝缘膜上沉积Ru，Ir或Pt的膜。 因此，根据防沉积膜或种子膜的图案形成下部电极。
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50.发明授权Process for making a semiconductor integrated circuit device having a dynamic random access memory 失效制造具有动态随机存取存储器的半导体集成电路器件的工艺公开(公告)号：US06426255B1
公开(公告)日：2002-07-30
申请号：US09549085
申请日：2000-04-13
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/2885 , H01L27/10814 , H01L27/10882 , H01L28/55 , H01L28/60
摘要： After formation of a groove in a silicon oxide film, a Pt film is formed inside of the groove by electroplating using a conductive underlying film, which has been formed in advance below the silicon oxide film, as a cathode electrode. The silicon oxide film is then removed by etching, followed by dry etching of the conductive underlying film with the Pt film as a mask, whereby a lower electrode of a capacitor is formed from the Pt film and the conductive underlying film which has remained below the Pt film.
摘要翻译： 在氧化硅膜中形成沟槽之后，通过使用在氧化硅膜之前预先形成的导电性底膜进行电镀而在沟槽内部形成Pt膜作为阴极电极。 然后通过蚀刻去除氧化硅膜，然后用Pt膜作为掩模对导电性底膜进行干蚀刻，由此由Pt膜和导电性底层膜形成电容器的下电极，该电极保持在低于 Pt膜。
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