公开(公告)号：US06664157B2

公开(公告)日：2003-12-16

申请号：US09775547

申请日：2001-02-05

申请人： Shinpei Iijima ,  Yoshitaka Nakamura ,  Masahiko Hiratani ,  Yuichi Matsui ,  Naruhiko Nakanishi

发明人： Shinpei Iijima ,  Yoshitaka Nakamura ,  Masahiko Hiratani ,  Yuichi Matsui ,  Naruhiko Nakanishi

IPC分类号： H01L218242

CPC分类号： H01L27/10855 ,  H01L27/10888 ,  H01L28/91

摘要： Plug electrodes of silicon are formed so as to be buried in through holes in a first insulating film, the plug electrodes being electrically connected to the source and drain regions of a MISFET on the main surface of a semiconductor substrate. Then, a second insulating film is deposited thereon and holes are formed therein such that the plug electrodes of silicon are exposed. A barrier film is formed on the surfaces of the silicon plugs, and in the holes a dielectric is formed to form lower electrodes of the capacitor elements and an upper electrode therefor.

摘要翻译： 形成硅的插入电极以埋在第一绝缘膜的通孔中，插塞电极与半导体衬底的主表面上的MISFET的源极和漏极区域电连接。 然后，在其上沉积第二绝缘膜，并在其中形成孔，使得硅的插塞电极露出。 在硅插头的表面上形成阻挡膜，并且在孔中形成电介质以形成电容器元件的下电极和用于其的上电极。

公开(公告)号：US06544834B1

公开(公告)日：2003-04-08

申请号：US09720002

申请日：2000-12-19

申请人： Yasuhiro Sugawara ,  Shinpei Iijima ,  Yuzuru Oji ,  Naruhiko Nakanishi ,  Misuzu Kanai ,  Masahiko Hiratani

发明人： Yasuhiro Sugawara ,  Shinpei Iijima ,  Yuzuru Oji ,  Naruhiko Nakanishi ,  Misuzu Kanai ,  Masahiko Hiratani

IPC分类号： H01L218242

CPC分类号： H01L27/1085 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/31604 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L28/40

摘要： An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.

摘要翻译： 集成半导体器件具有改进的可靠性并且适于更高的集成度，而不减少每个信息存储电容元件的累积电荷。 半导体器件具有DRAM，其具有存储单元，每个DRAM包括与形成在半导体衬底1的主表面上的存储单元选择MISFET Qs串联连接的信息存储电容元件C，具有下电极54，电容绝缘 膜58和上电极59.下电极54由在特定平面轴承（例如（002））面取向的钌膜制成，并且电容绝缘膜58由通过热处理得到的多晶钽膜制成 含有沉淀状态的结晶用氧化钽晶体的无定形氧化钽膜。

公开(公告)号：US06713343B2

公开(公告)日：2004-03-30

申请号：US10388618

申请日：2003-03-17

申请人： Yasuhiro Sugawara ,  Shinpei Iijima ,  Yuzuru Oji ,  Naruhiko Nakanishi ,  Misuzu Kanai ,  Masahiko Hiratani

发明人： Yasuhiro Sugawara ,  Shinpei Iijima ,  Yuzuru Oji ,  Naruhiko Nakanishi ,  Misuzu Kanai ,  Masahiko Hiratani

IPC分类号： H01L218242

CPC分类号： H01L27/1085 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/31604 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L28/40

摘要： An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.

摘要翻译： 集成半导体器件具有改进的可靠性并且适于更高的集成度，而不减少每个信息存储电容元件的累积电荷。 半导体器件具有DRAM，其具有存储单元，每个DRAM包括与形成在半导体衬底1的主表面上的存储单元选择MISFET Qs串联连接的信息存储电容元件C，具有下电极54，电容绝缘 膜58和上电极59.下电极54由在特定平面轴承（例如（002））面取向的钌膜制成，并且电容绝缘膜58由通过热处理得到的多晶钽膜制成 含有沉淀状态的结晶用氧化钽晶体的无定形氧化钽膜。

公开(公告)号：US06534375B2

公开(公告)日：2003-03-18

申请号：US09923406

申请日：2001-08-08

申请人： Shinpei Iijima ,  Yuzuru Ohji ,  Masato Kunitomo ,  Masahiko Hiratani ,  Yuichi Matsui ,  Hiroyuki Ohta ,  Yukihiro Kumagai

发明人： Shinpei Iijima ,  Yuzuru Ohji ,  Masato Kunitomo ,  Masahiko Hiratani ,  Yuichi Matsui ,  Hiroyuki Ohta ,  Yukihiro Kumagai

IPC分类号： H01L21285

CPC分类号： H01L21/02183 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/31637 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/91

摘要： A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.

摘要翻译： 形成在DRAM的电容元件的下部电极上形成的电介质膜的氧气氛中的氧气的缺点是氧气渗透下部电极氧化阻挡层以形成高电阻和低介电常数的氧化物层。 在形成在信息容纳电容元件C的下部电极下方的通孔中的插塞表面上形成Ru Ru硅化物层，并且在Ru硅化物层的表面上进一步形成Ru氮化硅层。 在下电极上形成电介质膜的步骤中进行的氧气氛中进行高温热处理时，将Ru氮化硅层牺牲性氧化为Ru氮氧化硅，以防止Ru化硅化物层的氧化进行。

公开(公告)号：US07259058B2

公开(公告)日：2007-08-21

申请号：US10020314

申请日：2001-12-18

申请人： Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Yuichi Matsui ,  Satoshi Yamamoto ,  Toshihide Nabatame ,  Toshio Ando ,  Hiroshi Sakuma ,  Shinpei Iijima

发明人： Yasuhiro Shimamoto ,  Masahiko Hiratani ,  Yuichi Matsui ,  Satoshi Yamamoto ,  Toshihide Nabatame ,  Toshio Ando ,  Hiroshi Sakuma ,  Shinpei Iijima

IPC分类号： H01L21/8242

CPC分类号： H01L28/60 ,  C23C16/18 ,  H01L21/28556 ,  H01L21/28568 ,  H01L28/55 ,  H01L28/91

摘要： A ruthenium electrode with a low amount of oxygen contamination and high thermal stability is formed by a chemical vapor deposition method. In the chemical vapor deposition method using an organoruthenium compound as a precursor, the introduction of an oxidation gas is limited to when the precursor is supplying, and the reaction is allowed to occur at a low oxygen partial pressure. Consequently, it is possible to form a ruthenium film with a low amount of oxygen contamination. Further, after formation of the ruthenium film, annealing at not less than the formation temperature is performed, thereby forming a ruthenium film with high thermal stability.

摘要翻译： 通过化学气相沉积法形成氧气污染少，热稳定性高的钌电极。 在使用有机钌化合物作为前体的化学气相沉积方法中，氧化气体的引入限于当前体供应时，并且允许反应在低氧分压下发生。 因此，可以形成氧含量低的钌膜。 此外，在形成钌膜之后，进行不低于形成温度的退火，由此形成热稳定性高的钌膜。

公开(公告)号：US06720603B2

公开(公告)日：2004-04-13

申请号：US10321614

申请日：2002-12-18

申请人： Shinpei Iijima ,  Yuzuru Ohji ,  Masato Kunitomo ,  Masahiko Hiratani ,  Yuichi Matsui ,  Hiroyuki Ohta ,  Yukihiro Kumagai

发明人： Shinpei Iijima ,  Yuzuru Ohji ,  Masato Kunitomo ,  Masahiko Hiratani ,  Yuichi Matsui ,  Hiroyuki Ohta ,  Yukihiro Kumagai

IPC分类号： H01L27108

CPC分类号： H01L21/02183 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/31637 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/60 ,  H01L28/91

摘要： A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.

摘要翻译： 形成在DRAM的电容元件的下部电极上形成的电介质膜的氧气氛中的氧气的缺点是氧气渗透下部电极氧化阻挡层以形成高电阻和低介电常数的氧化物层。 在形成在信息容纳电容元件C的下部电极下方的通孔中的插塞表面上形成Ru Ru硅化物层，并且在Ru硅化物层的表面上进一步形成Ru氮化硅层。 在下电极上形成电介质膜的步骤中进行的氧气氛中进行高温热处理时，将Ru氮化硅层牺牲性氧化为Ru氮氧化硅，以防止Ru化硅化物层的氧化进行。

公开(公告)号：US20050024811A1

公开(公告)日：2005-02-03

申请号：US10923002

申请日：2004-08-23

申请人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Shinpei Iijima ,  Isamu Asano ,  Yuzuru Ohji ,  Yoshitaka Nakamura

发明人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Shinpei Iijima ,  Isamu Asano ,  Yuzuru Ohji ,  Yoshitaka Nakamura

IPC分类号： H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01G4/008

CPC分类号： H01L28/60 ,  H01L27/10814 ,  H01L28/55

摘要： A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.

摘要翻译： 一种配备有信息存储电容器的半导体器件，包括第一电容器电极，氧化物膜，第二电容器电极和以硅为主要构成元素的绝缘膜，其中，第一和第二电容器电极中的至少一个包含作为主要构成元素 选自铑，钌，铱，锇和铂中的至少一种元素，并且作为添加元素，选自钯，镍，钴和钛中的至少一种元素，电容器电极和绝缘膜之间的粘附性优异。

公开(公告)号：US06927439B2

公开(公告)日：2005-08-09

申请号：US10923002

申请日：2004-08-23

申请人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Shinpei Iijima ,  Isamu Asano ,  Yuzuru Ohji ,  Yoshitaka Nakamura

发明人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Shinpei Iijima ,  Isamu Asano ,  Yuzuru Ohji ,  Yoshitaka Nakamura

IPC分类号： H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L28/60 ,  H01L27/10814 ,  H01L28/55

摘要： A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.

摘要翻译： 一种配备有信息存储电容器的半导体器件，包括第一电容器电极，氧化物膜，第二电容器电极和以硅为主要构成元素的绝缘膜，其中，第一和第二电容器电极中的至少一个包含作为主要构成元素 选自铑，钌，铱，锇和铂中的至少一种元素，并且作为添加元素，选自钯，镍，钴和钛中的至少一种元素，电容器电极和绝缘膜之间的粘附性优异。

公开(公告)号：US07183170B2

公开(公告)日：2007-02-27

申请号：US10998804

申请日：2004-11-30

申请人： Yoshitaka Nakamura ,  Tsuyoshi Kawagoe ,  Hiroshi Sakuma ,  Isamu Asano ,  Keiji Kuroki ,  Hidekazu Goto ,  Shinpei Iijima

发明人： Yoshitaka Nakamura ,  Tsuyoshi Kawagoe ,  Hiroshi Sakuma ,  Isamu Asano ,  Keiji Kuroki ,  Hidekazu Goto ,  Shinpei Iijima

IPC分类号： H01L21/20

CPC分类号： H01L28/65 ,  H01L21/32136 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L28/91

摘要： After an upper electrode protective film is formed such that it is in a firm contact with ruthenium film of the upper electrode without damaging the ruthenium film, the upper electrode is etched, thereby, a MIM capacitor is obtained in which leak current is not increased due to oxidation of the ruthenium film of the upper electrode.

摘要翻译： 在形成上部电极保护膜使得其与上部电极的钌膜牢固接触而不损坏钌膜之后，蚀刻上部电极，由此获得漏电流不增加的MIM电容器 以使上电极的钌膜氧化。

公开(公告)号：US20050118762A1

公开(公告)日：2005-06-02

申请号：US10998804

申请日：2004-11-30

申请人： Yoshitaka Nakamura ,  Tsuyoshi Kawagoe ,  Hiroshi Sakuma ,  Isamu Asano ,  Keiji Kuroki ,  Hidekazu Goto ,  Shinpei Iijima

发明人： Yoshitaka Nakamura ,  Tsuyoshi Kawagoe ,  Hiroshi Sakuma ,  Isamu Asano ,  Keiji Kuroki ,  Hidekazu Goto ,  Shinpei Iijima

IPC分类号： C23C16/40 ,  H01L21/02 ,  H01L21/316 ,  H01L21/3213 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L28/65 ,  H01L21/32136 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L28/91

摘要： After an upper electrode protective film is formed such that it is in a firm contact with ruthenium film of the upper electrode without damaging the ruthenium film, the upper electrode is etched, thereby, a MIM capacitor is obtained in which leak current is not increased due to oxidation of the ruthenium film of the upper electrode.

摘要翻译： 在形成上部电极保护膜使得其与上部电极的钌膜牢固接触而不损坏钌膜之后，蚀刻上部电极，由此获得漏电流不增加的MIM电容器 以使上电极的钌膜氧化。