公开(公告)号：US08631261B2

公开(公告)日：2014-01-14

申请号：US11967303

申请日：2007-12-31

申请人： Don A. Van Dyke ,  Michael Mishaeli ,  Ittai Anati ,  Baiju V. Patel ,  Will Deutsch ,  Rajesh Shah ,  Gilbert Neiger ,  James B. Crossland ,  Chris J. Newburn ,  Bryant E. Bigbee ,  Muhammad Faisal Azeem ,  John L. Reid ,  Dion Rodgers

发明人： Don A. Van Dyke ,  Michael Mishaeli ,  Ittai Anati ,  Baiju V. Patel ,  Will Deutsch ,  Rajesh Shah ,  Gilbert Neiger ,  James B. Crossland ,  Chris J. Newburn ,  Bryant E. Bigbee ,  Muhammad Faisal Azeem ,  John L. Reid ,  Dion Rodgers

IPC分类号： G06F1/32 ,  G06F9/44

CPC分类号： G06F9/30043 ,  G06F9/30003 ,  G06F9/30101 ,  G06F9/461

摘要： Embodiments of an invention related to context state management based on processor features are disclosed. In one embodiment, a processor includes instruction logic and state management logic. The instruction logic is to receive a state management instruction having a parameter to identify a subset of the features supported by the processor. The state management logic is to perform a state management operation specified by the state management instruction.

公开(公告)号：US20140013333A1

公开(公告)日：2014-01-09

申请号：US13993471

申请日：2011-12-28

申请人： Michael Mishaeli ,  James B. Crossland ,  Boris Ginzburg ,  Eliezer Weissmann

发明人： Michael Mishaeli ,  James B. Crossland ,  Boris Ginzburg ,  Eliezer Weissmann

IPC分类号： G06F9/46

CPC分类号： G06F9/461 ,  G06F9/44 ,  G06F9/445 ,  G06F9/46 ,  G06F9/48

摘要： Extended features such as registers and functions within processors are made available to operating systems (OS) using an extended-state driver and by modifying instruction set extensions, such as XSAVE. A map-table designates a correspondence between memory locations for storing data relating to extended features not supported by the OS and called by an application. As a result, applications may utilize processor resources which are unsupported by the OS.

摘要翻译： 扩展功能（如处理器内的寄存器和功能）可以使用扩展状态驱动程序和修改指令集扩展（如XSAVE）对操作系统（OS）可用。 映射表指定用于存储与OS不支持并被应用程序调用的扩展特征有关的数据的存储器位置之间的对应关系。 因此，应用程序可能利用OS不支持的处理器资源。

公开(公告)号：US08230203B2

公开(公告)日：2012-07-24

申请号：US11694344

申请日：2007-03-30

申请人： Gilbert Neiger ,  Randolph L. Campbell ,  James B. Crossland ,  Gideon Gerzon ,  Leena K. Puthiyedath ,  Stephen A. Fischer ,  Steven M. Bennett ,  Andrew V. Anderson

发明人： Gilbert Neiger ,  Randolph L. Campbell ,  James B. Crossland ,  Gideon Gerzon ,  Leena K. Puthiyedath ,  Stephen A. Fischer ,  Steven M. Bennett ,  Andrew V. Anderson

IPC分类号： G06F9/00 ,  G06F9/455

CPC分类号： G06F9/45533

摘要： Embodiments of apparatuses, methods, and systems detecting spin loops in a virtual machine environment are disclosed. In one embodiment, an apparatus includes detection logic and virtualization logic. The detection logic is to detect whether a guest is executing a spin loop. The virtualization logic is to transfer control of the apparatus from the guest to a host in response to the detection logic detecting that the guest is executing the spin loop.

摘要翻译： 公开了在虚拟机环境中检测自旋回路的装置，方法和系统的实施例。 在一个实施例中，装置包括检测逻辑和虚拟逻辑。 检测逻辑是检测访客是否正在执行自旋循环。 响应于检测到客户正在执行自旋回路的检测逻辑，虚拟化逻辑是将设备的控制从客户转移到主机。

公开(公告)号：US08122230B2

公开(公告)日：2012-02-21

申请号：US11966924

申请日：2007-12-28

申请人： Leena K. Puthiyedath ,  James B. Crossland ,  Martin G. Dixon ,  John G. Holm ,  Raicsh Parthasarathy

发明人： Leena K. Puthiyedath ,  James B. Crossland ,  Martin G. Dixon ,  John G. Holm ,  Raicsh Parthasarathy

IPC分类号： G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/30003 ,  G06F9/3851 ,  G06F9/3891

摘要： Embodiments of an invention for using a processor identification instruction to provide multi-level processor topology information are disclosed. In one embodiment, a processor includes decode logic and control logic. The decode logic is to receive an identification instruction having an associated topological level value. The control logic is to provide, in response to the decode logic receiving the identification instruction, processor identification information corresponding to the associated topological level value.

摘要翻译： 公开了使用处理器识别指令来提供多级处理器拓扑信息的发明的实施例。 在一个实施例中，处理器包括解码逻辑和控制逻辑。 解码逻辑是接收具有相关拓扑水平值的识别指令。 控制逻辑是响应于接收到识别指令的解码逻辑，提供对应于相关拓扑水平值的处理器识别信息。

公开(公告)号：US20080059711A1

公开(公告)日：2008-03-06

申请号：US11513871

申请日：2006-08-31

申请人： Francis X. McKeen ,  Leena K. Puthiyedath ,  Ernie Brickell ,  James B. Crossland

发明人： Francis X. McKeen ,  Leena K. Puthiyedath ,  Ernie Brickell ,  James B. Crossland

IPC分类号： G06F12/00

CPC分类号： G06F21/79 ,  G06F12/0804 ,  G06F12/0848 ,  G06F12/0891 ,  G06F12/126 ,  G06F12/1416 ,  G06F21/556

摘要： A method for managing a cache is disclosed. A context switch is identified. It is determined whether an application running after the context switch requires protection. Upon determining that the application requires protection the cache is partitioned. According to an aspect of the present invention, a partitioned section of the cache is completely over written with data associated with the application. Other embodiments are described and claimed.

摘要翻译： 公开了一种用于管理高速缓存的方法。 识别上下文切换。 确定在上下文切换后运行的应用程序是否需要保护。 在确定应用程序需要保护时，缓存被分区。 根据本发明的一个方面，高速缓存的分区部分完全被写入与应用相关的数据。 描述和要求保护其他实施例。

公开(公告)号：US07127561B2

公开(公告)日：2006-10-24

申请号：US10039656

申请日：2001-12-31

申请人： David L. Hill ,  Deborah T. Marr ,  Dion Rodgers ,  Shiv Kaushik ,  James B. Crossland ,  David A. Koufaty

发明人： David L. Hill ,  Deborah T. Marr ,  Dion Rodgers ,  Shiv Kaushik ,  James B. Crossland ,  David A. Koufaty

IPC分类号： G06F12/08

CPC分类号： G06F12/0808 ,  G06F12/0831

摘要： Coherency techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes a cache, execution logic to execute an instruction having an operand indicating a monitor address and a bus controller. In one embodiment, the bus controller is to assert a preventative signal in response to receiving a memory access attempting to gain sufficient ownership of a cache line associated with said monitor address to allow modification of said cache line without generation of another transaction indicative of the modification. In another embodiment, the bus controller is to generate a bus cycle in response to the instruction to eliminate any ownership of the cache line by another processor that would allow a modification of the cache line without generation of another memory access indicative of the modification.

公开(公告)号：US09317360B2

公开(公告)日：2016-04-19

申请号：US13995458

申请日：2011-12-29

申请人： Jose A. Vargas ,  Mohan J. Kumar ,  James B. Crossland ,  Murugasamy K. Nachimuthu ,  Theodros Yigzaw

发明人： Jose A. Vargas ,  Mohan J. Kumar ,  James B. Crossland ,  Murugasamy K. Nachimuthu ,  Theodros Yigzaw

IPC分类号： G06F11/00 ,  G06F11/08 ,  G06F11/22 ,  G06F11/10 ,  G06F11/07

CPC分类号： G06F11/1004 ,  G06F11/0724 ,  G06F11/0793

摘要： In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view.

摘要翻译： 在一些实现中，处理器可以包括具有多个错误报告寄存器的机器检查架构，其能够接收用于机器检查错误的数据。 总结寄存器可以包括多个可设置位置，每个位置可以代表错误报告寄存器中的至少一个。 可以将汇总寄存器中的一个或多个可设置位置设置为指示一个或多个错误报告寄存器是否保持机器检查错误的数据。 因此，当发生机器检查错误时，可以访问总结寄存器以识别处理器视图中的任何错误报告寄存器是否包含有效的错误数据，而不是在处理器视图中读取每个错误报告寄存器。

公开(公告)号：US08635415B2

公开(公告)日：2014-01-21

申请号：US12571269

申请日：2009-09-30

申请人： Baiju V. Patel ,  Rajeev Gopalakrishna ,  Andrew F. Glew ,  Robert J. Kushlis ,  Don Alan Van Dyke ,  Joseph Frank Cihula ,  Asit K. Mallick ,  James B. Crossland ,  Gilbert Neiger ,  Scott Dion Rodgers ,  Martin Guy Dixon ,  Mark Jay Charney ,  Jacob (Koby) Gottlieb

发明人： Baiju V. Patel ,  Rajeev Gopalakrishna ,  Andrew F. Glew ,  Robert J. Kushlis ,  Don Alan Van Dyke ,  Joseph Frank Cihula ,  Asit K. Mallick ,  James B. Crossland ,  Gilbert Neiger ,  Scott Dion Rodgers ,  Martin Guy Dixon ,  Mark Jay Charney ,  Jacob (Koby) Gottlieb

IPC分类号： G06F12/02 ,  G06F9/302

CPC分类号： G06F9/3013 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/32 ,  G06F9/342 ,  G06F9/35 ,  G06F12/1441

摘要： A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.

摘要翻译： 一组处理器的默认寄存器被扩展到计算机系统的处理器上的元数据寄存器。 存储有数据的默认寄存器，而与数据相关的元数据分别存储在元数据寄存器上。

公开(公告)号：US20140013045A1

公开(公告)日：2014-01-09

申请号：US13993344

申请日：2011-12-29

申请人： James B. Crossland ,  Toby Opferman ,  Blaise Fanning

发明人： James B. Crossland ,  Toby Opferman ,  Blaise Fanning

IPC分类号： G06F12/02

CPC分类号： G06F12/0638 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0866 ,  G06F2212/202 ,  G06F2212/2024 ,  G06F2212/205 ,  G11C7/1072 ,  G11C13/0004 ,  G11C14/0036 ,  G11C14/0045

摘要： A method and system are disclosed. In one embodiment the method includes allocating several memory locations within a phase change memory and switch (PCMS) memory to be utilized as a Random Access Memory (RAM) Disk. The RAM Disk is created for use by a software application running in a computer system. The method also includes mapping at least a portion of the allocated amount of PCMS memory to the software application address space. Finally, the method also grants the software application direct access to at least a portion of the allocated amount of the PCMS memory.

摘要翻译： 公开了一种方法和系统。 在一个实施例中，该方法包括在相变存储器和交换机（PCMS）存储器内分配若干存储器位置，以用作随机存取存储器（RAM）盘。 RAM磁盘被创建供在计算机系统中运行的软件应用程序使用。 该方法还包括将分配的PCMS存储器的至少一部分映射到软件应用地址空间。 最后，该方法还允许软件应用直接访问PCMS存储器的分配量的至少一部分。

公开(公告)号：US20130031333A1

公开(公告)日：2013-01-31

申请号：US13191327

申请日：2011-07-26

申请人： Rajesh M. Sankaran ,  Altug Koker ,  Philip R. Lantz ,  Asit K. Mallick ,  James B. Crossland ,  Aditya Navale ,  Gilbert Neiger ,  Andrew V. Anderson

发明人： Rajesh M. Sankaran ,  Altug Koker ,  Philip R. Lantz ,  Asit K. Mallick ,  James B. Crossland ,  Aditya Navale ,  Gilbert Neiger ,  Andrew V. Anderson

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F12/1081 ,  G06F2212/1016 ,  G06F2212/1048 ,  G06F2212/303 ,  G06F2212/682 ,  G06F2212/683

摘要： Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

摘要翻译： 公开了用于在多核系统中共享虚拟存储器的异构设备的有效TLB（转换后备缓冲器）击穿的方法和装置。 用于有效的TLB击倒的装置的实施例可以包括用于存储虚拟地址转换条目的TLB和与TLB耦合的存储器管理单元，以维护对应于虚拟地址转换条目的PASID（进程地址空间标识符）状态条目 。 PASID状态条目可以包括活动参考状态和惰性无效状态。 响应于从多核系统中的设备接收到PASID状态更新请求并且读取PASID状态条目的惰性无效状态，存储器管理单元可执行PASID状态条目的原子修改。 存储器管理单元可以在响应于相应的惰性无效化状态的激活之前向设备发送PASID状态更新响应以同步TLB条目。