公开(公告)号：US20160013774A1

公开(公告)日：2016-01-14

申请号：US14330464

申请日：2014-07-14

Applicant: QUALCOMM Incorporated

Inventor： Hee Jun Park ,  Dexter Tamio Chun

IPC: H03K3/012 ,  H03K3/011

CPC classification number: H03K3/012 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4074 ,  G11C11/4093 ,  H03K3/011

Abstract: Techniques for adjusting swing voltage for an I/O interface signal are described herein. In one embodiment, a device comprises an input/output (I/O) interface, and an I/O voltage controller. The I/O voltage controller is configured to determine a frequency or temperature of the I/O interface, and to adjust a swing voltage of the I/O interface based at least in part upon the determined frequency or temperature.

Abstract translation: 本文描述了用于调整I / O接口信号的摆动电压的技术。 在一个实施例中，设备包括输入/​​输出（I / O）接口和I / O电压控制器。 I / O电压控制器被配置为确定I / O接口的频率或温度，并且至少部分地基于所确定的频率或温度来调整I / O接口的摆幅电压。

公开(公告)号：US20150213850A1

公开(公告)日：2015-07-30

申请号：US14599768

申请日：2015-01-19

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  David Ian West

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F13/1678 ,  G06F13/4243 ,  G06F13/4295 ,  Y02D10/14 ,  Y02D10/151

Abstract: Serial data transmission for dynamic random access memory (DRAM) interfaces is disclosed. Instead of the parallel data transmission that gives rise to skew concerns, exemplary aspects of the present disclosure transmit the bits of a word serially over a single lane of the bus. Because the bus is a high speed bus, even though the bits come in one after another (i.e., serially), the time between arrival of the first bit and arrival of the last bit of the word is still relatively short. Likewise, because the bits arrive serially, skew between bits becomes irrelevant. The bits are aggregated within a given amount of time and loaded into the memory array.

Abstract translation: 公开了用于动态随机存取存储器（DRAM）接口的串行数据传输。 代替引起偏斜关系的并行数据传输，本公开的示例性方面在总线的单个通道上串行地传送字的位。 由于总线是高速总线，即使这些位一个接一个地（即，串行地）进入，第一位到达之间的时间和该字的最后一位的到达仍然相对较短。 同样，由于这些位串行到达，所以位之间的偏移变得无关紧要。 这些位在给定的时间内聚合并加载到存储器阵列中。

公开(公告)号：US11728003B2

公开(公告)日：2023-08-15

申请号：US17245981

申请日：2021-04-30

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Anand Srinivasan ,  Olivier Alavoine ,  Laurent Rene Moll

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C29/18 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C7/1045 ,  G11C29/18 ,  G11C29/44 ,  G11C2029/1202

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

公开(公告)号：US11662919B2

公开(公告)日：2023-05-30

申请号：US17494089

申请日：2021-10-05

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Michael Hawjing Lo ,  Shyamkumar Thoziyoor ,  Ravindra Kumar

IPC: G06F3/06 ,  G06F12/0875

CPC classification number: G06F3/0625 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0875 ,  G06F2212/1028 ,  G06F2212/45

Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

公开(公告)号：US11164618B2

公开(公告)日：2021-11-02

申请号：US16907103

申请日：2020-06-19

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Yanru Li ,  Michael Hawjing Lo ,  Dexter Tamio Chun

IPC: G11C5/00 ,  G11C11/406 ,  G11C7/10 ,  G11C8/12

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

公开(公告)号：US10956057B2

公开(公告)日：2021-03-23

申请号：US16115845

申请日：2018-08-29

Applicant: QUALCOMM Incorporated

Inventor： Yanru Li ,  Dexter Tamio Chun

IPC: G06F3/06

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of controlling a memory of a computing device by an adaptive memory controller. The method includes collecting usage data from the computing device over a first bin, wherein the first bin is associated with a first weight, wherein the first weight is indicative of one or more of a first partial array self-refresh (PASR) setting a first partial array auto refresh (PAAR) setting and a first deep power down (DPD) setting. The method further includes associating the collected data with a second weight, adapting the first bin based on the second weight, wherein the second weight is indicative of one or more of a second PASR, PAAR, and DPD setting. The method further includes controlling the memory during the next first bin based on the second weight.

公开(公告)号：US20190179399A1

公开(公告)日：2019-06-13

申请号：US16268634

申请日：2019-02-06

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Michael Hawjing Lo

IPC: G06F1/3234 ,  G06F13/42 ,  G06F12/06 ,  G11C7/10 ,  G06F13/16 ,  G06F1/3225

Abstract: Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state.

公开(公告)号：US20190129493A1

公开(公告)日：2019-05-02

申请号：US15798116

申请日：2017-10-30

Applicant: QUALCOMM INCORPORATED

Inventor： YANRU LI ,  Azzedine Touzni ,  Dexter Tamio Chun

IPC: G06F1/32 ,  G06F9/44 ,  G06F15/78

Abstract: Systems and methods are disclosed for managing memory access for low-power use cases of a system on chip. One such method comprises booting a system on chip (SoC) comprising a plurality of SoC processing devices. A trusted channel is created to a secure non-volatile random access memory (NVRAM). The method determines a power-saving software program to be executed on the SoC by one of the plurality of SoC processing devices. A software image associated with the power-saving software program is loaded to the secure NVRAM. In response to loading the software image to the secure NVRAM, each of the plurality of SoC processing devices except the one executing the software image from the secure NVRAM are powered down.

公开(公告)号：US10055284B2

公开(公告)日：2018-08-21

申请号：US15489621

申请日：2017-04-17

Applicant: QUALCOMM INCORPORATED

Inventor： Richard Alan Stewart ,  Dexter Tamio Chun

IPC: G06F11/10 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F11/1044 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246

Abstract: Systems, methods, and computer programs are disclosed for providing error detection or correction with flash cell mapping. One embodiment is a method comprising generating raw page data for a physical page in a main array of a flash memory device. The raw page data comprises less than a capacity of the physical page generated using a non-power-of-two flash cell mapping. One or more parity bits are generated for the raw page data using an error detection or correction scheme. The method stores the raw page data and the one or more parity bits in the physical page in the main array.

公开(公告)号：US09823846B2

公开(公告)日：2017-11-21

申请号：US14464598

申请日：2014-08-20

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Tamio Chun ,  Suryanarayana China Chittuluri ,  Yanru Li

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/10 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F3/0607 ,  G06F3/0631 ,  G06F3/0665 ,  G06F3/0683 ,  G06F12/0246 ,  G06F12/06 ,  G06F12/10 ,  G06F13/1684 ,  G06F2212/1048 ,  G06F2212/152 ,  G06F2212/171 ,  G06F2212/206 ,  G06F2212/214 ,  G06F2212/261 ,  G06F2212/654 ,  G06F2212/7201

Abstract: Systems and methods are disclosed for expanding memory for a system on chip (SoC). A memory card is loaded in an expandable memory socket electrically and is coupled to a system on chip (SoC) via an expansion bus. The memory card comprises a first volatile memory device. In response to detecting the memory card, an expanded virtual memory map is configured. The expanded virtual memory map comprises a first virtual memory space associated the first volatile memory device and a second virtual memory space associated with a second volatile memory device electrically coupled to the SoC via a memory bus. One or more peripheral images associated with the second virtual memory space are relocated to a first portion of the first virtual memory space. A second portion of the first virtual memory space is configured as a block device for performing swap operations associated with the second virtual memory space.