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    SEMICONDUCTOR DEVICE HAVING HIGH-FREQUENCY INTERCONNECT
    43.
    发明申请
    SEMICONDUCTOR DEVICE HAVING HIGH-FREQUENCY INTERCONNECT 有权
    具有高频互连的半导体器件

    公开(公告)号：US20130234286A1

    公开(公告)日：2013-09-12

    申请号：US13871448

    申请日：2013-04-26

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yasutaka NAKASHIBA

    IPC: H01L23/535

    CPC classification number: H01L23/535 ,  H01L23/522 ,  H01L23/5227 ,  H01L23/585 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided is a semiconductor device including high-frequency interconnect and dummy conductor patterns (second dummy conductor patterns). The dummy conductor patterns are disposed in a interconnect layer different from a interconnect layer in which the high-frequency interconnect is disposed. The dummy conductor patterns are disposed so as to keep away from a region overlapping the high-frequency interconnect in plan view. The semiconductor device further includes dummy conductor patterns (first dummy conductor patterns) in the interconnect layer in which the high-frequency interconnect is disposed.

    Abstract translation: 提供了包括高频互连和虚设导体图案（第二虚拟导体图案）的半导体器件。 虚设导体图案设置在与布置高频互连的互连层不同的互连层中。 虚设导体图案设置成在平面图中远离与高频互连重叠的区域。 半导体器件还包括配置有高频互连的互连层中的虚设导体图案（第一虚设导体图案）。

    SEMICONDUCTOR DEVICE
    44.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20130181324A1

    公开(公告)日：2013-07-18

    申请号：US13788542

    申请日：2013-03-07

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yasutaka NAKASHIBA

    IPC: H01L27/04

    CPC classification number: H01L23/5227 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5383 ,  H01L24/48 ,  H01L24/49 ,  H01L27/04 ,  H01L28/10 ,  H01L2224/05553 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

    Abstract: A semiconductor device sends and receives electrical signals. The semiconductor device includes a first substrate provided with a first circuit region containing a first circuit; a multi-level interconnect structure provided on the first substrate; a first inductor provided in the multi-level interconnect structure so as to include the first circuit region; and a second inductor provided in the multi-level interconnect structure so as to include the first circuit region, wherein one of the first inductor and the second inductor is connected to the first circuit and the other of the first inductor and the second inductor is connected to a second circuit.

    Abstract translation: 半导体器件发送和接收电信号。 半导体器件包括：第一衬底，设置有包含第一电路的第一电路区域; 设置在所述第一基板上的多级互连结构; 设置在所述多电平互连结构中以便包括所述第一电路区域的第一电感器; 以及设置在所述多电平互连结构中的第二电感器，以便包括所述第一电路区域，其中所述第一电感器和所述第二电感器中的一个连接到所述第一电路，并且所述第一电感器和所述第二电感器中的另一个被连接 到第二电路。

    SEMICONDUCTOR DEVICE
    45.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20130175636A1

    公开(公告)日：2013-07-11

    申请号：US13682591

    申请日：2013-01-04

    Applicant: Renesas Electronics Corporation

    Inventor： Yasutaka NAKASHIBA

    IPC: H01L27/06

    CPC classification number: H01L27/0617 ,  H01L23/5227 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a substrate, a transistor formed over the substrate, insulating layers formed over the substrate, a multilayer wiring formed in the insulating layers, a first inductor formed in the insulating layers, and a second inductor formed over the first inductor and overlapping the first inductor. The insulating layers contain a silicon, wherein at least the two insulating layers are formed between the first inductor and the second inductor, and the first inductor and the second inductor are a spiral wiring pattern.

    Abstract translation: 半导体器件包括衬底，形成在衬底上的晶体管，形成在衬底上的绝缘层，形成在绝缘层中的多层布线，形成在绝缘层中的第一电感器，以及形成在第一电感器上并重叠的第二电感器 第一个电感。 绝缘层包含硅，其中至少两个绝缘层形成在第一电感器和第二电感器之间，并且第一电感器和第二电感器是螺旋布线图案。

    SEMICONDUCTOR DEVICE
    46.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250054884A1

    公开(公告)日：2025-02-13

    申请号：US18932997

    申请日：2024-10-31

    Applicant: Renesas Electronics Corporation

    Inventor： Tohru KAWAI ,  Yasutaka NAKASHIBA

    IPC: H01L23/64 ,  H01F27/00

    Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer, a first inductor, a second insulating layer, a second inductor, a pad and an annular wiring. The first insulating layer is formed on the semiconductor substrate. The first inductor is directly formed on the first insulating layer. The second insulating layer is formed on the first insulating layer such that the second insulating layer covers the first inductor. The second inductor is directly formed on the second insulating layer such that the second inductor faces the first inductor. The pad is directly formed on the second insulating layer. The pad is electrically connected with the second inductor. The annular wiring is electrically connected with the pad. The annular wiring is spaced apart from the second inductor. The annular wiring surrounds the second inductor without forming a vertex in plan view.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    47.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20240371817A1

    公开(公告)日：2024-11-07

    申请号：US18311561

    申请日：2023-05-03

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yasutaka NAKASHIBA ,  Toshiyuki HATA

    IPC: H01L23/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/495

    Abstract: A semiconductor device includes: a first semiconductor chip mounted on a chip mounting portion via a first bonding material; and a second semiconductor chip mounted on the first semiconductor chip via a second bonding material. The first semiconductor chip includes: a protective film; and a first pad electrode exposed from the protective film in a first opening portion of the protective film. The second semiconductor chip is mounted on the first pad electrode of the first semiconductor chip via the second bonding material. The second bonding material includes: a first member being in contact with the first pad electrode; and a second member interposed between the first member and the second semiconductor chip. The first member is a conductive bonding material of a film shape, and the second member is an insulating bonding material of a film shape.

    SEMICONDUCTOR DEVICE
    48.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240304524A1

    公开(公告)日：2024-09-12

    申请号：US18664117

    申请日：2024-05-14

    Applicant: Renesas Electronics Corporation

    Inventor： Tohru KAWAI ,  Yasutaka NAKASHIBA

    IPC: H01L23/485 ,  H01L29/872

    CPC classification number: H01L23/485 ,  H01L29/872

    Abstract: A semiconductor device includes a semiconductor substrate, a buried insulating film, a first conductive film, an insulating layer, a first contact and a second contact. The semiconductor substrate includes a first semiconductor region having a first conductive type and a second semiconductor region having a second conductive type. The buried insulating film surrounds the second semiconductor region in plan view. The first conductive film directly contacts with the first and second semiconductor regions. The first and second contacts overlap with the second semiconductor region in plan view and reach the first conductive film. The first contact is adjacent to the second contact along a first side of the second semiconductor region in plan view. In a direction along the first side, a first distance between the second semiconductor region and the buried insulating film is greater than a second distance between the first contact and the second contact.

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