公开(公告)号：US5869357A

公开(公告)日：1999-02-09

申请号：US681621

申请日：1996-07-29

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L29/417 ,  H01L29/78 ,  H01L21/283

CPC classification number: H01L24/05 ,  H01L21/76838 ,  H01L24/03 ,  H01L24/48 ,  H01L29/41741 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05073 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/49107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14

Abstract: A metallization and bonding process for manufacturing a power semiconductor device includes a step of depositing a first metal layer over the entire surface of a chip; a step of selectively etching of the first metal layer to form desired patterns of metal interconnection lines between components previously defined; a step of depositing a layer of passivating material over the entire surface of the chip; a step of selectively etching of the layer of passivating material down to the first metal layer to define bonding areas represented by uncovered portions of the first metal layer; a step of depositing of a thick second metal layer over the entire surface of the chip; a step of selectively etching of the second metal layer down to the layer of passivating material to remove the second metal layer outside the bonding areas; and a step of connecting bonding wires to the surface of the second metal layer in correspondence of said bonding areas.

Abstract translation: 用于制造功率半导体器件的金属化和接合工艺包括在芯片的整个表面上沉积第一金属层的步骤; 选择性地蚀刻第一金属层以形成之前定义的部件之间的金属互连线的期望图案的步骤; 在芯片的整个表面上沉积钝化材料层的步骤; 将钝化材料层选择性地蚀刻到第一金属层的步骤，以限定由第一金属层的未覆盖部分表示的结合区域; 在芯片的整个表面上沉积厚的第二金属层的步骤; 选择性地将第二金属层蚀刻到钝化材料层以除去接合区域外的第二金属层的步骤; 以及对应于所述接合区域将接合线连接到第二金属层的表面的步骤。

公开(公告)号：US5866461A

公开(公告)日：1999-02-02

申请号：US801584

申请日：1997-02-18

Applicant: Santo Puzzolo ,  Raffaele Zambrano ,  Mario Paparo

Inventor： Santo Puzzolo ,  Raffaele Zambrano ,  Mario Paparo

IPC: H01L27/07 ,  H01L27/082 ,  H01L21/8228

CPC classification number: H01L27/0744 ,  H01L27/0823

Abstract: A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N- epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides a connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.

Abstract translation: 双极功率晶体管和低电压双极晶体管以集成结构组合在发射极开关或半谐振器配置中。 在具有非隔离部件的版本中，结构的部件彼此完全或部分地叠置，部分地在第一外延层中，部分地叠置在第二外延层中，并且低电压双极晶体管位于 双极功率晶体管因此是完全埋入的有源结构。 在具有隔离元件的版本中，在N-外延层中有两个P +区。 第一P +区域构成功率晶体管基极并且包围功率晶体管的N +发射极区域。 第二P +区域包围分别构成低压晶体管的集电极，发射极和基极区域的两个N +区域和一个P +区域。 芯片前面的金属化提供了低压晶体管的集电极触点和功率晶体管的发射极触点之间的连接。

公开(公告)号：US5796157A

公开(公告)日：1998-08-18

申请号：US547881

申请日：1995-10-25

Applicant: Giuseppe Fallico ,  Raffaele Zambrano

Inventor： Giuseppe Fallico ,  Raffaele Zambrano

IPC: H01L29/735 ,  H01L29/00

CPC classification number: H01L29/735

Abstract: A high-frequency lateral PNP transistor includes a base region laterally delimited by P type emitter and collector regions, and at the top by a surface portion of the N type semiconductor body housing the active area of the transistor. The surface portion delimiting the base region presents no formations of insulating material grown across the surface, so that the width (W.sub.B) of the base region is reduced and ensures optimum dynamic characteristics of the transistor. The base contact may be located directly over the surface portion facing the base region, to reduce the extrinsic base resistance and overall size of the device, or it may be located remotely and connected to the base region by a buried layer and sinker region to further reduce the base width.

Abstract translation: 高频横向PNP晶体管包括由P型发射极和集电极区域横向界定的基极区域，并且在顶部由N型半导体器件的表面部分容纳晶体管的有源区域。 限定基部区域的表面部分不存在跨越表面生长的绝缘材料的形成，使得基极区域的宽度（WB）减小并且确保晶体管的最佳动态特性。 基部触点可以直接位于面向基底区域的表面部分上方，以减小外部基极电阻和器件的整体尺寸，或者可以远程定位并通过掩埋层和沉降片区域连接到基极区域以进一步 减小底宽。

公开(公告)号：US5773899A

公开(公告)日：1998-06-30

申请号：US705921

申请日：1996-08-29

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L29/417 ,  H01L29/78 ,  H01L23/48 ,  H01L29/43 ,  H01L21/784

CPC classification number: H01L24/05 ,  H01L21/76838 ,  H01L24/03 ,  H01L24/48 ,  H01L29/41741 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05073 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/49107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14

Abstract: Disclosed is a bonding pad for a semiconductor chip which prevents damage during a bonding process. In a semiconductor chip having conductive regions interconnected by a metal pattern, a metal region is disposed over the metal pattern. The metal region forms a bonding pad area over the conductive regions. In addition, the metal region is in direct contact with the metal pattern for substantially the whole bonding pad area. With this arrangement, the metal region absorbs mechanical stress induced when a bonding wire is bonded to the metal region during a bonding process. The metal region is sufficiently thick so as not to be perforated during the bonding process and the metal pattern is, therefore, not damaged.

Abstract translation: 公开了一种用于半导体芯片的焊盘，其防止在接合过程中的损坏。 在具有通过金属图案互连的导电区域的半导体芯片中，金属区域设置在金属图案之上。 金属区域在导电区域上形成焊盘区域。 此外，金属区域与金属图案直接接触，用于基本上整个焊盘区域。 通过这种布置，金属区域在接合工艺期间吸收在接合线与金属区域接合时引起的机械应力。 金属区域足够厚，以便在接合过程中不被穿孔，因此金属图案不被损坏。

公开(公告)号：US5652455A

公开(公告)日：1997-07-29

申请号：US241010

申请日：1994-05-11

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L23/62

CPC classification number: H01L27/0255 ,  H01L2924/0002

Abstract: An integrated structure protection circuit suitable for protecting a power device against overvoltages comprises a plurality of serially connected junction diodes, each having a first electrode, represented by a highly doped region of a first conductivity type, and a second electrode represented by a medium doped or low doped region of a second conductivity type. A first diode of said plurality has its first electrode connected to a gate layer of said power device and its second electrode connected to the second electrode of at least one second diode of said plurality, and said at least one second diode has its first electrode connected to a drain region of the power device. The doping level of the second electrode of the diodes of said plurality is suitable to achieve sufficiently high breakdown voltage values.

Abstract translation: 适用于保护功率器件免受过电压的集成结构保护电路包括多个串联连接的结二极管，每个具有第一电极，由第一导电类型的高掺杂区域表示，第二电极由介质掺杂或 第二导电类型的低掺杂区域。 所述多个第一二极管的第一电极连接到所述功率器件的栅极层，其第二电极连接到所述多个第一二极管的第二电极，并且所述至少一个第二二极管的第一电极连接 到功率器件的漏极区域。 所述多个二极管的第二电极的掺杂水平适于实现足够高的击穿电压值。

公开(公告)号：US5631177A

公开(公告)日：1997-05-20

申请号：US380725

申请日：1995-01-30

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L21/33

CPC classification number: H01L29/66712 ,  H01L21/823456 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/0847 ,  H01L29/42368

Abstract: A manufacturing process for an integrated circuit which includes at least one vertical-current-flow MOS transistor. The patterned photoresist which screens the body implant is also used to mask the etching of a nitride layer over a pad oxide. After the photoresist is cleared, the nitride pattern is transferred into the oxide, and the resulting oxide/nitride stack is used to mask the source implant. The nitride/oxide stack is then removed, the gate oxide is grown, and the gate layer is then deposited.

Abstract translation: 一种用于集成电路的制造方法，该集成电路包括至少一个垂直电流流量MOS晶体管。 屏蔽体植入物的图案化光致抗蚀剂还用于掩蔽衬垫氧化物上的氮化物层的蚀刻。 在光致抗蚀剂被清除之后，氮化物图案被转移到氧化物中，并且所得到的氧化物/氮化物堆叠用于掩蔽源植入物。 然后去除氮化物/氧化物堆叠，生长栅极氧化物，然后沉积栅极层。

公开(公告)号：US5489799A

公开(公告)日：1996-02-06

申请号：US265059

申请日：1994-06-28

Applicant: Raffaele Zambrano ,  Salvatore Leonardi ,  Giovanna Cacciola

Inventor： Raffaele Zambrano ,  Salvatore Leonardi ,  Giovanna Cacciola

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/76 ,  H01L29/06 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC classification number: H01L29/66295 ,  H01L29/0615 ,  H01L29/1004

Abstract: An integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region of a first conductivity type extending from a semiconductor device top surface is described. The edge structure comprises a first, lightly doped ring of the first conductivity type obtained in a first, lightly doped epitaxial layer of a second conductivity type and surrounding said diffused region, and a second, lightly doped ring of the first conductivity type, comprising at least one portion superimposed on and merged with said first ring, obtained in a second, lightly doped epitaxial layer of the second conductivity type grown over the first epitaxial layer.

Abstract translation: 描述了一种用于高电压半导体器件的集成边缘结构，其包括由从半导体器件顶表面延伸的第一导电类型的扩散区域表示的PN结。 该边缘结构包括第一导电类型的第一轻掺杂环，其在第二导电类型的第一轻掺杂外延层中并且包围所述扩散区，以及第二导电类型的第二轻掺杂环，包括 在第一外延层上生长的第二导电类型的第二轻掺杂外延层中获得的至少一个部分叠加在所述第一环上并与之合并。

公开(公告)号：US5432376A

公开(公告)日：1995-07-11

申请号：US869760

申请日：1992-04-16

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/76 ,  H01L21/331 ,  H01L21/74 ,  H01L21/761 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L27/102 ,  H01L29/70

CPC classification number: H01L21/74 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/0823

Abstract: The base region of the power stage and the horizontal isolation region of the integrated control circuit or collector region of a transistor of an integrated circuit consist of portions of an epitaxial layer with a first conductivity type grown in sequence on an underlying epitaxial layer with a second conductivity type opposite the first.

Abstract translation: 功率级的基极区域和集成电路的晶体管的集成控制电路或集电极区域的水平隔离区域由具有第一导电类型的外延层的部分依次生长在下面的外延层上，具有第二 导电类型与第一种相反。

公开(公告)号：US5376821A

公开(公告)日：1994-12-27

申请号：US812704

申请日：1991-12-23

Applicant: Santo Puzzolo ,  Raffaele Zambrano ,  Mario Paparo

Inventor： Santo Puzzolo ,  Raffaele Zambrano ,  Mario Paparo

IPC: H01L21/8249 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L27/07

CPC classification number: H01L27/0823 ,  H01L21/8222 ,  H01L27/0825

Abstract: A bipolar power transistor and a low voltage bipolar transistor are combined in an emitter switching or a semibridge configuration in an integrated structure. In a version with non-isolated components, the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer, and the low voltage bipolar transistor is situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In a version with isolated components, there are two P+ regions in an N-epitaxial layer. The first P+ region constitutes the power transistor base and encloses the N+ emitter region of the power transistor. The second P+ region encloses two N+ regions and one P+ region, constituting the collector, emitter, and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides a connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.

Abstract translation: 双极功率晶体管和低电压双极晶体管以集成结构组合在发射极开关或半谐振器配置中。 在具有非隔离部件的版本中，结构的部件彼此完全或部分地叠置，部分地在第一外延层中，部分地叠置在第二外延层中，并且低电压双极晶体管位于 双极功率晶体管因此是完全埋入的有源结构。 在具有隔离元件的版本中，N外延层中有两个P +区。 第一P +区域构成功率晶体管基极并且包围功率晶体管的N +发射极区域。 第二P +区域包围分别构成低压晶体管的集电极，发射极和基极区域的两个N +区域和一个P +区域。 芯片前面的金属化提供了低压晶体管的集电极触点和功率晶体管的发射极触点之间的连接。

公开(公告)号：US4889822A

公开(公告)日：1989-12-26

申请号：US241269

申请日：1988-09-07

Applicant: Salvatore Musumeci ,  Raffaele Zambrano

Inventor： Salvatore Musumeci ,  Raffaele Zambrano

IPC: H01L21/331 ,  H01L21/74 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732

CPC classification number: H01L21/761 ,  H01L21/74 ,  H01L21/8222

Abstract: The invention concerns a process for manufacturing a monolithic integrated semiconductor device comprising an integrated control circuit and high-voltage power components. It solves the problem of undesired phantom layers created by out diffusion of the type-P dopant present in the insulation region of the substrate. Between a first epitaxial layer and a third epitaxial layer of the device, a second epitaxial layer is grown of predetermined thickness, and a first region for the insulation of the integrated control citcuit is formed in the first epitaxial layer and at least a second region for the buried layer is formed in the second eiptaxial layer.