公开(公告)号：US06518613B2

公开(公告)日：2003-02-11

申请号：US09968304

申请日：2001-10-01

Applicant: Josef Willer ,  Hans Reisinger ,  Till Schlosser ,  Reinhard Stengl

Inventor： Josef Willer ,  Hans Reisinger ,  Till Schlosser ,  Reinhard Stengl

IPC: H01L27108

CPC classification number: H01L27/10864 ,  H01L27/10867 ,  H01L27/1087

Abstract: A MOS transistor of a memory cell and a bit line connected thereto are disposed on a first surface of a substrate. A capacitor of the memory cell is disposed on a second surface of the substrate, the second surface being opposite to the first surface. A contact is disposed in the substrate and connects the capacitor to the MOS transistor.

Abstract translation: 存储单元的MOS晶体管和与其连接的位线设置在基板的第一表面上。 存储单元的电容器设置在基板的第二表面上，第二表面与第一表面相对。 接触件设置在衬底中并将电容器连接到MOS晶体管。

公开(公告)号：US06495439B1

公开(公告)日：2002-12-17

申请号：US09819062

申请日：1999-06-22

Applicant: Jeffrey Peter Gambino ,  Son Van Nguyen ,  Reinhard Stengl

Inventor： Jeffrey Peter Gambino ,  Son Van Nguyen ,  Reinhard Stengl

IPC: H01L2128

CPC classification number: H01L21/02164 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/76801 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10T428/24926 ,  H01L2924/00

Abstract: Significant amounts of pattern distortion were found to be the result of reflowing borophosphosilicate glass (BPSG) and silicon dioxide shrinkage during high temperature junction anneals. In order to remedy this problem, a method for suppressing the pattern distortion by subjecting the wafer coated with BPSG and with silicon dioxide layers to a high temperature anneal before patterning is disclosed. The high temperature anneal densifies the undoped silicon dioxide before patterning, so that shrinkage of the undoped silicon dioxide does not affect the patterning steps.

Abstract translation: 发现大量的图案变形是在高温结合退火期间回流硼磷硅酸盐玻璃（BPSG）和二氧化硅收缩的结果。 为了解决这个问题，公开了一种通过在涂布图案之前对涂覆有BPSG的晶片和二氧化硅层进行高温退火来抑制图案变形的方法。 在图案化之前，高温退火使未掺杂的二氧化硅致密化，使得未掺杂二氧化硅的收缩不影响图案化步骤。

公开(公告)号：US6037209A

公开(公告)日：2000-03-14

申请号：US254696

申请日：1999-03-15

Applicant: Wolfgang Rosner ,  Lothar Risch ,  Franz Hofmann ,  Reinhard Stengl

Inventor： Wolfgang Rosner ,  Lothar Risch ,  Franz Hofmann ,  Reinhard Stengl

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10823

Abstract: The DRAM cell arrangement comprises, per memory cell, a vertical MOS transistor whose first source/drain region is connected to a storage node of a storage capacitor, whose channel region (3) is annularly enclosed by a gate electrode (13) and whose second source/drain region is connected to a buried bit line. The DRAM cell arrangement is produced using only two masks, with the aid of a spacer technique, with a memory cell area of 2F.sup.2, where F is the minimum structure size which can be produced using the respective technology.

Abstract translation: PCT No.PCT / DE97 / 01580 Sec。 371 1999年3月15日 102（e）1999年3月15日PCT 1997年7月28日PCT公布。 出版物WO98 / 11604 日期1998年3月19日DRAM单元布置包括每个存储单元的垂直MOS晶体管，其第一源极/漏极区域连接到存储电容器的存储节点，其沟道区域（3）被栅电极环形封闭 13），并且其第二源极/漏极区域连接到掩埋位线。 借助于间隔器技术，仅使用两个掩模来制造DRAM单元布置，存储单元面积为2F2，其中F是可以使用各自技术产生的最小结构尺寸。

公开(公告)号：US5844266A

公开(公告)日：1998-12-01

申请号：US879871

申请日：1997-06-20

Applicant: Reinhard Stengl ,  Erwin Hammerl ,  Herbert L. Ho ,  Jack A. Mandelman ,  Radhika Srinivasan ,  Alvin P. Short

Inventor： Reinhard Stengl ,  Erwin Hammerl ,  Herbert L. Ho ,  Jack A. Mandelman ,  Radhika Srinivasan ,  Alvin P. Short

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC classification number: H01L27/10861 ,  H01L27/10832

Abstract: In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

Abstract translation: 在用于在DRAM单元中的沟槽存储电容器和存取晶体管之间进行电连接的方法中，通过选择性地控制存在于沟槽中的N型或P型掺杂剂的扩散，通过单晶 半导体材料，其通过从沟槽侧壁外延（epi）生长。 该外延生长的单晶层作为在常规DRAM的处理中可能发生的过量掺杂剂扩散扩散的障碍。

公开(公告)号：US5360759A

公开(公告)日：1994-11-01

申请号：US123605

申请日：1993-09-17

Applicant: Reinhard Stengl ,  Wolfgang Hoenlein ,  Volker Lehmann ,  Andreas Spitzer

Inventor： Reinhard Stengl ,  Wolfgang Hoenlein ,  Volker Lehmann ,  Andreas Spitzer

IPC: H01L21/28 ,  H01L21/306 ,  H01L31/11 ,  H01L33/34 ,  H01L21/283 ,  H01L21/265

CPC classification number: H01L33/346 ,  H01L21/306 ,  H01L31/1105 ,  Y10S438/96

Abstract: For manufacturing a component with porous silicon, two highly doped regions with a lightly doped region arranged between them are formed in a silicon wafer. The dopant concentrations are thereby set such that porous silicon arises in the lightly doped region in a subsequent anodic etching. Light-emitting diodes or light-controlled bipolar transistors can be manufactured in this way.

Abstract translation: 为了制造具有多孔硅的部件，在硅晶片中形成具有布置在它们之间的轻掺杂区域的两个高掺杂区域。 因此，掺杂剂浓度被设定为使得随后的阳极蚀刻在轻掺杂区域中产生多孔硅。 可以以这种方式制造发光二极管或光控双极晶体管。

公开(公告)号：US4672738A

公开(公告)日：1987-06-16

申请号：US776161

申请日：1985-09-13

Applicant: Reinhard Stengl ,  Ulrich Goesele ,  Christine Fellinger

Inventor： Reinhard Stengl ,  Ulrich Goesele ,  Christine Fellinger

IPC: H01L21/033 ,  H01L21/22 ,  H01L21/265 ,  H01L21/266 ,  H01L29/06 ,  H01L29/74

CPC classification number: H01L21/0334 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0688 ,  Y10S148/01 ,  Y10S438/965

Abstract: A method for the manufacture of a pn junction having a high breakdown voltage at the boundary surface of a semiconductor body, utilizing a mask which has a relatively large opening for introducing a dopant therethrough into the semiconductor body, the mask having a marginal edge which extends laterally beyond the edge of the relatively large opening. In the marginal edge, the mask is provided with smaller, auxiliary openings, the openings being sized and spaced such that lesser amounts of dopant pass through the opening as the distance of the auxiliary openings from the edge of the relatively larger opening increases. Upon introducing the dopant into the semiconductor body through the mask, there is generated a doping profile which gradually approaches the boundary surface with increasing distance from the edge of the relatively large opening.

Abstract translation: 一种用于制造在半导体本体的边界表面具有高击穿电压的pn结的方法，利用具有相对较大的开口的掩模，用于将掺杂剂引入到半导体本体中，所述掩模具有延伸的边缘 横向超过相对较大开口的边缘。 在边缘处，掩模设置有较小的辅助开口，开口的尺寸和间隔使得当辅助开口距相对较大开口的边缘的距离增加时，较少量的掺杂剂通过开口。 当通过掩模将掺杂剂引入半导体本体时，产生掺杂分布，其随着距离相对大的开口的边缘的距离增加而逐渐接近边界表面。

公开(公告)号：US08003475B2

公开(公告)日：2011-08-23

申请号：US12051928

申请日：2008-03-20

Applicant: Josef Böck ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer ,  Martin Seck

Inventor： Josef Böck ,  Rudolf Lachner ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer ,  Martin Seck

IPC: H01L21/331

CPC classification number: H01L29/66272 ,  H01L21/8222 ,  H01L27/0825 ,  H01L29/0821

Abstract: A method for fabricating a transistor structure with a first and a second bipolar transistor having different collector widths is presented. The method includes providing a semiconductor substrate, introducing a first buried layer of the first bipolar transistor and a second buried layer of the second bipolar transistor into the semiconductor substrate, and producing at least a first collector region having a first collector width on the first buried layer and a second collector region having a second collector width on the second buried layer. A first collector zone having a first thickness is produced on the second buried layer for production of the second collector width. A second collector zone having a second thickness is produced on the first collector zone. At least one insulation region is produced that isolates at least the collector regions from one another.

Abstract translation: 提出了一种制造具有不同集电极宽度的第一和第二双极晶体管的晶体管结构的方法。 该方法包括提供半导体衬底，将第一双极晶体管的第一掩埋层和第二双极晶体管的第二掩埋层引入到半导体衬底中，并且至少在第一掩埋层上产生具有第一集电极宽度的第一集电极区域 层和在第二掩埋层上具有第二集电极宽度的第二集电极区。 在第二掩埋层上产生具有第一厚度的第一收集器区，用于产生第二收集器宽度。 在第一收集器区域上产生具有第二厚度的第二收集器区域。 产生至少一个绝缘区域，其至少隔离收集器区域彼此。

公开(公告)号：US07968972B2

公开(公告)日：2011-06-28

申请号：US12716692

申请日：2010-03-03

Applicant: Josef Böck ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer

Inventor： Josef Böck ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer

IPC: H01L29/73

CPC classification number: H01L29/66272 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/732

Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

Abstract translation: 高频双极晶体管包括邻接发射极连接区域的发射极接触件，邻接基极连接区域的基极接触件和邻接集电极连接区域的集电极接触件。 第一绝缘层设置在基底连接区域上。 集电极连接区域包含埋设层，该埋层将集电极触点连接到集电区。 在掩埋层上提供硅化物或自对准硅化物区域，并以低阻抗方式将集电极触点连接到集电极区域。 第二绝缘层设置在集电极连接区域上，但不在硅化物区域上。

公开(公告)号：US20110042046A1

公开(公告)日：2011-02-24

申请号：US12940713

申请日：2010-11-05

Applicant: Volker Lehmann ,  Reinhard Stengl ,  Herbert Schäfer

Inventor： Volker Lehmann ,  Reinhard Stengl ,  Herbert Schäfer

IPC: F28D15/04 ,  H01L21/306

CPC classification number: H01L23/473 ,  H01L21/30604 ,  H01L21/3063 ,  H01L23/427 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is provided. At least one integrated electronic component is arranged at a main area of a substrate. The component is arranged in the substrate or is isolated from the substrate by an electrically insulating region. Main channels are formed in the substrate and arranged along the main area. Each main channel is completely surrounded by the substrate transversely with respect to a longitudinal axis. Transverse channels are arranged transversely with respect to the main channels. Each transverse channel opens into at least one main channel. More than about ten transverse channels open into a main channel.

Abstract translation: 提供一种集成电路装置及其制造方法。 至少一个集成电子部件布置在基板的主要区域。 该部件布置在基板中，或者通过电绝缘区域与基板隔离。 主通道形成在基板上并且沿着主区域布置。 每个主通道相对于纵向轴线横向地完全被基底包围。 横向通道相对于主通道横向布置。 每个横向通道打开至少一个主通道。 超过十个横向通道进入主通道。

公开(公告)号：US07719088B2

公开(公告)日：2010-05-18

申请号：US11254502

申请日：2005-10-20

Applicant: Josef Böck ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer

Inventor： Josef Böck ,  Thomas Meister ,  Reinhard Stengl ,  Herbert Schäfer

IPC: H01L29/72

CPC classification number: H01L29/66272 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/732

Abstract: A high-frequency bipolar transistor includes an emitter contact adjoining an emitter connection region, a base contact adjoining a base connection region, and a collector contact adjoining a collector connection region. A first insulation layer is disposed on the base connection region. The collector connection region contains a buried layer, which connects the collector contact to a collector zone. A silicide or salicide region is provided on the buried layer and connects the collector contact to the collector zone in a low-impedance manner. A second insulation layer is disposed on the collector connection region but not on the silicide region.

Abstract translation: 高频双极晶体管包括邻接发射极连接区域的发射极接触件，邻接基极连接区域的基极接触件和邻接集电极连接区域的集电极接触件。 第一绝缘层设置在基底连接区域上。 集电极连接区域包含埋设层，该埋层将集电极触点连接到集电区。 在掩埋层上提供硅化物或自对准硅化物区域，并以低阻抗方式将集电极触点连接到集电极区域。 第二绝缘层设置在集电极连接区域上，但不在硅化物区域上。