公开(公告)号：US4621411A

公开(公告)日：1986-11-11

申请号：US656048

申请日：1984-09-28

申请人： Robert H. Havemann ,  Vernon R. Porter

发明人： Robert H. Havemann ,  Vernon R. Porter

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L21/26 ,  H01L21/268 ,  H01L21/336 ,  H01L21/263 ,  H01L21/265

CPC分类号： H01L21/268 ,  H01L21/2254 ,  Y10S148/091

摘要： Optical illumination rather than furnace heating is used to drive in MOSFET source and drain diffusions, preferably using a surface layer of antimony as the dopant source. This results in substantially less overlap between the gate and the source and drain diffusions. Similarly, if the present invention is practiced in a process having gate sidewalls less than zero overlap can be achieved.

摘要翻译： 使用光学照明而不是炉加热来驱动MOSFET源极和漏极扩散，优选使用锑的表面层作为掺杂剂源。 这导致栅极和源极和漏极扩散之间的重叠相当少。 类似地，如果本发明在具有小于零的栅极侧壁的工艺中实现，则可以实现重叠。

公开(公告)号：US4597164A

公开(公告)日：1986-07-01

申请号：US646600

申请日：1984-08-31

申请人： Robert H. Havemann

发明人： Robert H. Havemann

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L21/265

CPC分类号： H01L21/76202 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/763 ,  Y10S148/082 ,  Y10S438/966

摘要： Isolation trenches are formed around selected areas on an integrated circuit device, and highly doped areas are formed in the epitaxial silicon surrounding such trenches. The device is then oxidized at a low temperature, and differential oxidation growth of the highly doped areas causes a thick field oxide to grow outside the trenches while only a thin oxide grows over the selected areas.

摘要翻译： 在集成电路器件上的选定区域周围形成隔离沟槽，并且在围绕这样的沟槽的外延硅中形成高掺杂区域。 然后该器件在低温下被氧化，并且高掺杂区域的差异氧化生长导致厚场氧化物在沟槽外部生长，而只有一薄层氧化物在所选择的区域上生长。

公开(公告)号：US06753563B2

公开(公告)日：2004-06-22

申请号：US10001472

申请日：2001-11-01

申请人： Robert H. Havemann

发明人： Robert H. Havemann

IPC分类号： H01L2972

CPC分类号： H01L21/7682 ,  H01L21/3115 ,  H01L21/31695 ,  H01L21/76828 ,  H01L21/76829

摘要： In one aspect of the invention, a method for forming an integrated circuit having an at least substantially doped porous dielectric includes forming a semiconductor device. The semiconductor device includes at least a portion of a semiconductor substrate. The method also includes forming a dielectric layer disposed outwardly from the semiconductor substrate and surrounding at least a portion of the semiconductor device. The dielectric layer includes an at least substantially porous dielectric material doped with at least one dopant. In addition, the method includes forming a contact layer disposed outwardly from the dielectric layer and operable to provide electrical connection to the semiconductor device.

摘要翻译： 在本发明的一个方面，一种用于形成具有至少基本上掺杂的多孔电介质的集成电路的方法包括形成半导体器件。 半导体器件包括半导体衬底的至少一部分。 该方法还包括形成从半导体衬底向外设置并围绕半导体器件的至少一部分的电介质层。 电介质层包括掺杂有至少一种掺杂剂的至少基本上多孔的介电材料。 此外，该方法包括形成从电介质层向外设置的接触层，并可操作以提供与半导体器件的电连接。

公开(公告)号：US06753250B1

公开(公告)日：2004-06-22

申请号：US10171289

申请日：2002-06-12

申请人： Richard S. Hill ,  Willibrordus Gerardus Maria van den Hoek ,  Robert H. Havemann

发明人： Richard S. Hill ,  Willibrordus Gerardus Maria van den Hoek ,  Robert H. Havemann

IPC分类号： H01L214763

CPC分类号： H01L21/7682 ,  H01L2221/1047

摘要： Porous dielectric layers are produced by introducing small vertical or columnar gaps in pre-formed layers of dense dielectric. The pores may be formed by a special process that is different from the processes employed to form metal lines and other features on a VLSI device. Further, the columnar gaps may be produced after the planarization process for a particular layer has been completed. Then, after the pores are formed, they are capped by depositing another layer of material. In this manner, the newly porous layer is protected from direct exposure to the pressure of subsequent planarization processes. In alternative embodiments, the processes described herein are applied to introduce pores into a preformed layer of semiconductor to produce a porous semiconductor layer.

摘要翻译： 通过在致密电介质的预先形成的层中引入小的垂直或柱状间隙来产生多孔电介质层。 可以通过与用于在VLSI器件上形成金属线和其它特征的工艺不同的特殊工艺形成孔。 此外，在特定层的平坦化处理已经完成之后可以产生柱状间隙。 然后，在形成孔之后，通过沉积另一层材料来封盖它们。 以这种方式，保护新的多孔层免于直接暴露于随后的平坦化工艺的压力。 在替代实施例中，应用本文所述的方法将孔导入预制的半导体层以产生多孔半导体层。

公开(公告)号：US06566211B2

公开(公告)日：2003-05-20

申请号：US10008143

申请日：2001-11-08

申请人： Carole D. Graas ,  Robert H. Havemann

发明人： Carole D. Graas ,  Robert H. Havemann

IPC分类号： H01L21336

CPC分类号： H01L21/76885 ,  H01L21/28044 ,  H01L21/28114 ,  H01L21/76886 ,  H01L23/26 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/4941 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure having refractory sidewalls 240 for enhanced yield, performance and reliability. The primary purpose of the refractory metal 240 is to getter sidewall impurities, residual polymers, and corrosive species by-products from the plasma etch and cleanup processes used to pattern interconnects. In a preferred embodiment, the refractory metal 240 reacts with the conducting layer 210 to form an intermetallic 245 which further enhances the endurance of the metallization against stress-induced rupturing and via-induced electromigration. The disclosed structures and methods are particularly advantageous in “zero-overlap” designs, and aggressive pitch patterns where linewidth and corrosion control are critical, but are also advantageous in “Damascene” pattern definition applications.

公开(公告)号：US06278174B1

公开(公告)日：2001-08-21

申请号：US08845340

申请日：1997-04-25

申请人： Robert H. Havemann ,  Manoj K. Jain

发明人： Robert H. Havemann ,  Manoj K. Jain

IPC分类号： H01L2358

CPC分类号： H01L23/5222 ,  H01L21/02131 ,  H01L21/02134 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/3121 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76837 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An intermetal level dielectric with two different low dielectric constant insulators: one for gap filling (140) within a metal level and the other (150) for between metal levels. Preferred embodiments include HSQ (140) as the gap filling low dielectric constant insulator and fluorinated silicon oxide (150) as the between metal level low dielectric constant insulator.

摘要翻译： 具有两个不同的低介电常数绝缘体的金属间电平介质：一个用于在金属层内的间隙填充（140），另一个用于金属层之间（150）。 优选实施例包括作为间隔填充低介电常数绝缘体的HSQ（140）和作为金属级低介电常数绝缘体之间的氟化氧化硅（150）。

公开(公告)号：US5814558A

公开(公告)日：1998-09-29

申请号：US658401

申请日：1996-06-04

申请人： Shin-puu Jeng ,  Robert H. Havemann

发明人： Shin-puu Jeng ,  Robert H. Havemann

IPC分类号： H01L23/52 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/441

CPC分类号： H01L21/02118 ,  H01L21/02137 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/7682 ,  H01L21/76837 ,  H01L23/5222 ,  H01L23/53223 ,  H01L21/76834 ,  H01L2924/0002

摘要： A semiconductor device and method for manufacturing same, having a low-dielectric constant material between metal leads in order to decrease unwanted capacitance. A metal layer 114 is deposited on a substrate 112. Metal leads 116 are formed in the metal layer 114. An oxide liner 118 is deposited on the metal leads 116, where the oxide liner 118 has a greater thickness on the tops of the metal leads 116 than on the sides of metal leads. A low-dielectric constant material 120 is deposited over the oxide liner 118 between the metal leads 116, where the low-dielectric constant material 120 is a material with a dielectric constant of less than 3.5.

摘要翻译： 一种半导体器件及其制造方法，在金属引线之间具有低介电常数材料，以减少不需要的电容。 金属层114沉积在基板112上。金属引线116形成在金属层114中。氧化物衬垫118沉积在金属引线116上，其中氧化物衬垫118在金属引线的顶部上具有更大的厚度 116比在金属引线的侧面。 低介电常数材料120沉积在金属引线116之间的氧化物衬垫118上，其中低介电常数材料120是介电常数小于3.5的材料。

公开(公告)号：US5472913A

公开(公告)日：1995-12-05

申请号：US286761

申请日：1994-08-05

申请人： Robert H. Havemann ,  Bruce E. Gnade ,  Chih-Chen Cho

发明人： Robert H. Havemann ,  Bruce E. Gnade ,  Chih-Chen Cho

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/02216 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/02359 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/53223 ,  H01L2221/1047 ,  H01L2924/0002

摘要： A semiconductor device and process for making the same are disclosed which use porous dielectric materials to reduce capacitance between conductors, while allowing conventional photolithography and metal techniques and materials to be used in fabrication. In one structure, patterned conductors 18 are provided on an interlayer dielectric 10, with a substrate encapsulation layer 32 deposited conformally over this structure. A layer of porous dielectric material 22 (e.g. dried SiO.sub.2 gel) is then deposited to substantially fill the gaps between and also cover the conductors. A substantially solid cap layer 24 of a material such as SiO.sub.2 is then deposited, followed by a photolithography step to define via locations. Vias are etched through the cap layer, and then through the porous dielectric. A via passivating layer 30 is conformally deposited and then anisotropically etched to clear the bottom of the vias while leaving a passivating liner in the via, preventing the via metal from directly contacting the porous material. A second application of these steps may be used to form a second, overlying structure of patterned conductors 38, encapsulating layer 36, porous dielectric layer 40, and cap layer 42.

摘要翻译： 公开了一种半导体器件及其制造方法，其使用多孔介电材料来减小导体之间的电容，同时允许常规光刻和金属技术和材料用于制造。 在一个结构中，图案化导体18设置在层间电介质10上，基底封装层32保形地沉积在该结构上。 然后沉积一层多孔电介质材料22（例如干燥的SiO 2凝胶）以基本上填充导体之间的间隙并且还覆盖导体。 然后沉积诸如SiO 2的材料的基本上固体的盖层24，然后沉积光刻步骤以限定通孔位置。 通孔通过盖层蚀刻，然后通过多孔电介质。 通孔钝化层30被共形沉积，然后各向异性蚀刻以清除通孔的底部，同时在通孔中留下钝化衬垫，防止通孔金属直接接触多孔材料。 可以使用这些步骤的第二应用来形成图案化导体38，封装层36，多孔介电层40和盖层42的第二覆盖结构。

公开(公告)号：US5465005A

公开(公告)日：1995-11-07

申请号：US14890

申请日：1993-02-08

申请人： Robert H. Eklund ,  Robert H. Havemann ,  Leo Stroth

发明人： Robert H. Eklund ,  Robert H. Havemann ,  Leo Stroth

IPC分类号： H01L21/02 ,  H01C8/00

CPC分类号： H01L28/20

摘要： An integrated circuit device including at least one polysilicon resistor 10 is disclosed herein. A polysilicon layer 24 is formed, possibly over a field oxide 12. The polysilicon layer 24 is then doped to achieve a selected sheet resistance. An insulating layer 18 (e.g., an oxide, a nitride, or a combination thereof) is then formed over the polysilicon layer 24. The insulating layer 18 is patterned and etched to define a resistor body 14 in the underlying polysilicon layer 24. The polysilicon layer 24 is then patterned and etched to define first and second resistor heads 16 abutting the resistor body 14 while simultaneously at least one polysilicon element 28 of a second electronic device is formed. Other systems and methods are also disclosed.

摘要翻译： 本文公开了包括至少一个多晶硅电阻器10的集成电路器件。 形成多晶硅层24，可能在场氧化物12上方。然后掺杂多晶硅层24以获得选定的薄层电阻。 然后在多晶硅层24上形成绝缘层18（例如，氧化物，氮化物或其组合）。图案化和蚀刻绝缘层18以在下面的多晶硅层24中限定电阻体14。 然后对层24进行构图和蚀刻以限定邻接电阻体14的第一和第二电阻头16，同时形成第二电子器件的至少一个多晶硅元件28。 还公开了其它系统和方法。

公开(公告)号：US5217924A

公开(公告)日：1993-06-08

申请号：US644855

申请日：1991-01-22

申请人： Mark S. Rodder ,  Robert H. Havemann

发明人： Mark S. Rodder ,  Robert H. Havemann

IPC分类号： H01L21/225 ,  H01L21/285

CPC分类号： H01L21/2257 ,  H01L21/2253 ,  H01L21/28518 ,  Y10S148/019

摘要： A method for forming a shallow junction (56) with a relatively thick metal silicide (52) thereover is provided. A first relatively thin layer (38) of a metal is deposited over the surface of a semiconductor substrate. An impurity (40) is then implanted (42) into or through the first layer (38). A relatively thick second layer (48) of metal is deposited over the first layer (38). An anneal process (50) is then performed to out-diffuse the impurities (40) from the first layer (38) into the substrate (32). The anneal also forms a combined metal silicide (52) from the first layer (38) and the second layer (48). The junction (56) thus formed has less surface damage, reduced spiking and reduced implant straggle than junctions formed according to the prior art. An alternate technique is also disclosed wherein an implant into or through a silicide layer is utilized.

摘要翻译： 提供了一种用于形成其上具有相对厚的金属硅化物（52）的浅结（56）的方法。 第一相对较薄的金属层（38）沉积在半导体衬底的表面上。 然后将杂质（40）（42）注入或穿过第一层（38）。 相对较厚的金属第二层（48）沉积在第一层（38）上。 然后执行退火工艺（50）以将杂质（40）从第一层（38）扩散到衬底（32）中。 退火还形成来自第一层（38）和第二层（48）的组合的金属硅化物（52）。 由此形成的结（56）具有比根据现有技术形成的结更少的表面损伤，减少的尖峰和减少的植入物分裂。 还公开了一种替代技术，其中利用了进入或穿过硅化物层的植入物。