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182 条记录 (耗时 0.032 秒)

    Offset cancellation in a capacitively coupled amplifier
    41.
    发明授权
    Offset cancellation in a capacitively coupled amplifier 有权
    电容耦合放大器中的偏移消除

    公开(公告)号：US08102203B2

    公开(公告)日：2012-01-24

    申请号：US11860693

    申请日：2007-09-25

    申请人： Robert J. Drost ,  Robert Proebsting ,  Arlene Proebsting, legal representative ,  Scott M. Fairbanks ,  Ronald Ho

    发明人： Robert J. Drost ,  Robert Proebsting ,  Scott M. Fairbanks ,  Ronald Ho

    IPC分类号： H03F1/02

    CPC分类号： H03F3/45973 ,  H03F1/30

    摘要： A method for calibrating an offset voltage of an amplifier used to amplify capacitively coupled communication signals is described. During this process, a common voltage is applied to one or more inputs to the amplifier. Next, an output of the amplifier is iteratively, measured, and charge is applied to the one or more inputs until the offset voltage is less than a pre-determined value. Note that applying the charge may involve applying a sequence of one or more charge pulses.

    摘要翻译： 描述了用于校准用于放大电容耦合通信信号的放大器的偏移电压的方法。 在该过程中，将公共电压施加到放大器的一个或多个输入。 接下来，迭代地，测量放大器的输出，并且将电荷施加到一个或多个输入，直到偏移电压小于预定值。 注意，应用电荷可以包括应用一个或多个充电脉冲的序列。

    APPARATUS FOR REDUCING POWER CONSUMPTION BY USING CAPACITIVE COUPLING TO PERFORM MAJORITY DETECTION
    42.
    发明申请
    APPARATUS FOR REDUCING POWER CONSUMPTION BY USING CAPACITIVE COUPLING TO PERFORM MAJORITY DETECTION 有权
    通过使用电容耦合来降低功耗以实现主要检测的设备

    公开(公告)号：US20120007699A1

    公开(公告)日：2012-01-12

    申请号：US13235152

    申请日：2011-09-16

    申请人： Ronald Ho ,  Robert J. Drost ,  Robert Hopkins

    发明人： Ronald Ho ,  Robert J. Drost ,  Robert Hopkins

    IPC分类号： H03H7/00

    CPC分类号： G06F1/189

    摘要： One embodiment of the present invention provides a system that reduces power consumption by using capacitive coupling to perform a majority detection operation. The system starts by driving a plurality of signals onto a plurality of driven wires. The signals are then fed from each driven wire through a corresponding coupling capacitor to a single majority detection wire. Next, the system feeds signal on the majority detection wire and a bias voltage to a differential receiver. The output of the differential receiver switches if the signal on the majority-detection wire switches relative to the bias voltage. The system then uses the output of the differential receiver to optimize the signals from the plurality of driven wires for transmission across a long signal route. Optimizing the transmission of signals reduces the power consumed by the computer system.

    摘要翻译： 本发明的一个实施例提供一种通过使用电容耦合来执行多数检测操作来降低功耗的系统。 系统通过将多个信号驱动到多个从动线上开始。 然后，这些信号从每个从动导线通过相应的耦合电容器馈送到单个多数检测线。 接下来，系统将多数检测线上的信号馈送到差分接收器的偏置电压。 如果多数检测线上的信号相对于偏置电压切换，差分接收器的输出将切换。 然后，系统使用差分接收器的输出来优化来自多条驱动线的信号，以便在长信号路径上传输。 优化信号传输减少了计算机系统消耗的功耗。

    Aperture generating circuit for a multiplying delay-locked loop
    43.
    发明授权
    Aperture generating circuit for a multiplying delay-locked loop 有权
    用于倍增延迟锁定环路的光圈产生电路

    公开(公告)号：US07994832B2

    公开(公告)日：2011-08-09

    申请号：US12613936

    申请日：2009-11-06

    申请人： Tamer M. Ali ,  Robert J. Drost ,  Chih-Kong Ken Yang

    发明人： Tamer M. Ali ,  Robert J. Drost ,  Chih-Kong Ken Yang

    IPC分类号： H03L7/00

    CPC分类号： H03L7/16 ,  H03L7/0816

    摘要： A multiplying delay-locked loop (MDLL) is described. In the MDLL, a phase interpolator (PI) provides a correction signal to selection control logic by phase mixing two internal signals (which have different phases) from a sequence of delay elements in the MDLL. This correction signal compensates for a delay associated with the selection control logic, thereby ensuring that a selection pulse or signal output by the selection control logic to a selection circuit (such as a multiplexer) is appropriately timed so that the selection circuit can selectively injection lock the sequence of delay elements using edges in a reference signal.

    摘要翻译： 描述了乘法延迟锁定环路（MDLL）。 在MDLL中，相位插值器（PI）通过将两个内部信号（其具有不同相位）与来自MDLL中的延迟元件的序列相混合来向选择控制逻辑提供校正信号。 该校正信号补偿与选择控制逻辑相关联的延迟，从而确保由选择控制逻辑输出到选择电路（例如多路复用器）的选择脉冲或信号被适当地定时，使得选择电路可以选择性地注入锁定 在参考信号中使用边缘的延迟元件的序列。

    OPTICAL CONNECTOR WITH REDUCED MECHANICAL-ALIGNMENT SENSITIVITY
    46.
    发明申请
    OPTICAL CONNECTOR WITH REDUCED MECHANICAL-ALIGNMENT SENSITIVITY 有权
    具有降低机械对准灵敏度的光学连接器

    公开(公告)号：US20100329607A1

    公开(公告)日：2010-12-30

    申请号：US12495228

    申请日：2009-06-30

    申请人： Robert J. Drost ,  John E. Cunningham ,  Ashok V. Krishnamoorthy

    发明人： Robert J. Drost ,  John E. Cunningham ,  Ashok V. Krishnamoorthy

    IPC分类号： G02B6/34 ,  G02B6/26

    CPC分类号： G02B6/4204 ,  G02B6/30 ,  G02B6/34 ,  G02B6/4215 ,  G02B6/4298 ,  G02B6/43

    摘要： An optical connector is described. This optical connector spatially segregates optical coupling between an optical fiber and an optical component, which relaxes the associated mechanical-alignment requirements. In particular, the optical connector includes an optical spreader component disposed on a substrate. This optical spreader component is optically coupled to the optical fiber at a first coupling region, and is configured to optically couple to the optical component at a second coupling region that is at a different location on the substrate than the first coupling region. Moreover, the first coupling region and the second coupling region are optically coupled by an optical waveguide.

    摘要翻译： 描述光连接器。 该光学连接器在空间上分离光纤和光学部件之间的光学耦合，这松弛了相关的机械对准要求。 特别地，光连接器包括设置在基板上的光扩散部件。 该光扩散器部件在第一耦合区域光学耦合到光纤，并且被配置为在与第一耦合区域在基板上的不同位置处的第二耦合区域光学耦合到光学部件。 此外，第一耦合区域和第二耦合区域通过光波导光学耦合。

    Method and apparatus for fabricating semiconductor chips using varying areas of precision
    48.
    发明授权
    Method and apparatus for fabricating semiconductor chips using varying areas of precision 有权
    使用不同精度的区域制造半导体芯片的方法和装置

    公开(公告)号：US07763396B2

    公开(公告)日：2010-07-27

    申请号：US11355757

    申请日：2006-02-16

    申请人： David C. Douglas ,  Ronald Ho ,  Robert J. Drost

    发明人： David C. Douglas ,  Ronald Ho ,  Robert J. Drost

    IPC分类号： G03F9/00

    CPC分类号： G03F7/70433

    摘要： A system that fabricates a semiconductor chip. The system places patterns for components which require fine line-widths within a high resolution region of a reticle, wherein the high resolution region provides sharp focus for a given wavelength of light used by the lithography system. At the same time, the system places patterns for components which do not require fine line-widths outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region. Note that the coarseness for components placed outside of the high resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high resolution region.

    摘要翻译： 制造半导体芯片的系统。 系统将要求精细线宽的部件的图案放置在标线的高分辨率区域内，其中高分辨率区域为光刻系统使用的给定波长的光提供清晰的焦点。 同时，系统将不需要精细线宽的部件的图案放置在标线片的高分辨率区域之外，从而利用分划板的高分辨率区域之外的区域，而不是避开该区域。 注意，放大在分划板的高分辨率区域之外的分量的粗糙度被增加以补偿高分辨率区域外的光学焦点的损失。

    Multi-phase clocking of integrated circuits using photonics
    49.
    发明授权
    Multi-phase clocking of integrated circuits using photonics 有权
    使用光子学的集成电路的多相时钟

    公开(公告)号：US07747173B1

    公开(公告)日：2010-06-29

    申请号：US11728841

    申请日：2007-03-26

    申请人： Ronald Ho ,  John E. Cunningham ,  Ashok V. Krishnamoorthy ,  Robert J. Drost

    发明人： Ronald Ho ,  John E. Cunningham ,  Ashok V. Krishnamoorthy ,  Robert J. Drost

    IPC分类号： H04B10/00

    CPC分类号： H04B10/801

    摘要： Embodiments of an integrated circuit are described. This integrated circuit includes a clock-generator circuit configured to provide a clock signal and an optical clock path coupled to the clock-generator circuit. Note that the optical clock path is configured to distribute optical signals corresponding to the clock signal. Furthermore, note that a given optical signal has a phase which is different than phases of the other optical signals.

    摘要翻译： 描述集成电路的实施例。 该集成电路包括时钟发生器电路，其被配置为提供时钟信号和耦合到时钟发生器电路的光时钟通路。 注意，光时钟路径被配置为分配对应于时钟信号的光信号。 此外，注意，给定的光信号具有与其它光信号的相位不同的相位。

    Structures and methods for an application of a flexible bridge
    50.
    发明授权
    Structures and methods for an application of a flexible bridge 有权
    应用柔性桥梁的结构和方法

    公开(公告)号：US07671449B2

    公开(公告)日：2010-03-02

    申请号：US11418986

    申请日：2006-05-04

    申请人： Arthur R. Zingher ,  Bruce M. Guenin ,  Ronald Ho ,  Robert J. Drost

    发明人： Arthur R. Zingher ,  Bruce M. Guenin ,  Ronald Ho ,  Robert J. Drost

    IPC分类号： H01L39/00 ,  H01L21/00

    CPC分类号： H01L23/5387 ,  H01L23/48 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2225/06562 ,  H01L2924/01067 ,  H01L2924/15311 ,  H01R12/62 ,  H05K3/222 ,  H05K2201/1053 ,  H05K2201/10674

    摘要： One embodiment of the present invention provides a system that facilitates high-bandwidth communication using a flexible bridge. This system includes a chip with an active face upon which active circuitry and signal pads reside, and a second component with a surface upon which active circuitry and/or signal pads reside. A flexible bridge provides high-bandwidth communication between the active face of the chip and the surface of the second component. This flexible bridge provides a flexible connection that allows the chip to be moved with six degrees of freedom relative to the second component without affecting communication between the chip and the second component. Hence, the flexible bridge allows the chip and the second component to communicate without requiring precise alignment between the chip and the second component.

    摘要翻译： 本发明的一个实施例提供一种促进使用柔性桥的高带宽通信的系统。 该系统包括具有有源电路和信号焊盘所在的有源面的芯片，以及具有有源电路和/或信号焊盘所在的表面的第二部件。 柔性桥提供芯片的有源面与第二部件的表面之间的高带宽通信。 该柔性桥提供柔性连接，允许芯片相对于第二部件以六个自由度移动，而不影响芯片和第二部件之间的通信。 因此，柔性桥允许芯片和第二部件通信，而不需要芯片和第二部件之间的精确对准。