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    SEMICONDUCTOR MEMORY DEVICES
    41.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20190051652A1

    公开(公告)日：2019-02-14

    申请号：US15952308

    申请日：2018-04-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung Kim ,  Min Hee Cho ,  Bong-Soo Kim ,  Junsoo Kim ,  Satoru Yamada ,  Wonsok Lee ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L29/06 ,  H01L29/49 ,  H01L21/28

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

    Semiconductor Device
    42.
    发明申请
    Semiconductor Device 审中-公开

    公开(公告)号：US20180294264A1

    公开(公告)日：2018-10-11

    申请号：US15827231

    申请日：2017-11-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung Uk Han ,  Taek Yong Kim ,  Satoru Yamada ,  Jun Hee Lim ,  Ki Jae Hur

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/762

    Abstract: A semiconductor device includes first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, wherein the first and second active regions overlaps with each other in the second direction, a third active region extending in the first direction on the substrate and spaced apart from the first active region in the second direction. The first active region is positioned between the second and third active regions in the second direction. The first and third active regions partially overlap in the second direction, and a device isolation film is configured to define the first to third active regions.

    Capacitorless memory device
    45.
    发明授权
    Capacitorless memory device 有权
    无电容存储器件

    公开(公告)号：US08941173B2

    公开(公告)日：2015-01-27

    申请号：US13775586

    申请日：2013-02-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung-Uk Han ,  Jae-Hoon Lee ,  Jun-Su Kim ,  Satoru Yamada ,  Jin-Seong Lee ,  Nam-Ho Jeon

    IPC: H01L29/66 ,  H01L27/088 ,  H01L27/11 ,  H01L27/108

    CPC classification number: H01L27/088 ,  H01L27/108 ,  H01L27/11

    Abstract: According to an example embodiment of inventive concepts, a capacitorless memory device includes a capacitorless memory cell that includes a bit line on a substrate; a read transistor, and a write transistor. The read transistor may include first to third impurity layers stacked in a vertical direction on the bit line. The first and third layers may be a first conductive type, and the second impurity layer may be a second conductive type that differs from the first conductive type. The write transistor may include a source layer, a body layer, and a drain layer stacked in the vertical direction on the substrate, and a gate line that is adjacent to a side surface of the body layer. The gate line may be spaced apart from the side surface of the body layer. The source layer may be adjacent to a side surface of the second impurity layer.

    Abstract translation: 根据本发明构思的示例性实施例，一种无电容器存储器件包括：无电容器存储器单元，其在衬底上包括位线; 读取晶体管和写入晶体管。 读取晶体管可以包括在位线上沿垂直方向堆叠的第一至第三杂质层。 第一和第三层可以是第一导电类型，并且第二杂质层可以是不同于第一导电类型的第二导电类型。 写入晶体管可以包括在基板上沿垂直方向堆叠的源极层，主体层和漏极层，以及与主体层的侧表面相邻的栅极线。 栅极线可以与主体层的侧表面间隔开。 源极层可以与第二杂质层的侧表面相邻。

    Semiconductor devices including semiconductor pattern
    46.
    发明授权
    Semiconductor devices including semiconductor pattern 有权

    公开(公告)号：US12191136B2

    公开(公告)日：2025-01-07

    申请号：US18098174

    申请日：2023-01-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Huijung Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

    IPC: H01L29/74 ,  H10B12/10

    Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

    Semiconductor memory device and method for fabricating thereof
    48.
    发明授权
    Semiconductor memory device and method for fabricating thereof 有权

    公开(公告)号：US11711918B2

    公开(公告)日：2023-07-25

    申请号：US17227793

    申请日：2021-04-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyung Hwan Lee ,  Yong Seok Kim ,  Hyun Cheol Kim ,  Satoru Yamada ,  Sung Won Yoo ,  Jae Ho Hong

    IPC: H10B41/70 ,  H10B41/20 ,  H10B41/35 ,  H10B41/41 ,  H10B41/50

    CPC classification number: H10B41/70 ,  H10B41/20 ,  H10B41/35 ,  H10B41/41 ,  H10B41/50

    Abstract: Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern.

    SEMICONDUCTOR DEVICES INCLUDING SEMICONDUCTOR PATTERN
    49.
    发明公开
    SEMICONDUCTOR DEVICES INCLUDING SEMICONDUCTOR PATTERN 审中-公开

    公开(公告)号：US20230163132A1

    公开(公告)日：2023-05-25

    申请号：US18098174

    申请日：2023-01-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Huijung Kim ,  Satoru Yamada ,  Sungwon Yoo ,  Kyunghwan Lee ,  Jaeho Hong

    IPC: H01L27/102 ,  H01L29/74

    CPC classification number: H01L27/1027 ,  H01L29/742

    Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

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