公开(公告)号：US20190006386A1

公开(公告)日：2019-01-03

申请号：US16004890

申请日：2018-06-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Takanori MATSUZAKI ,  Kiyoshi KATO ,  Satoru OKAMOTO

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

公开(公告)号：US20180248010A1

公开(公告)日：2018-08-30

申请号：US15903097

申请日：2018-02-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Hideomi SUZAWA ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Satoru OKAMOTO

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L29/49 ,  H01L29/423 ,  H01L27/146

CPC classification number: H01L29/78696 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1211 ,  H01L27/1225 ,  H01L27/1288 ,  H01L27/14616 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/785 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78693 ,  H01L2029/42388

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

公开(公告)号：US20180138213A1

公开(公告)日：2018-05-17

申请号：US15870182

申请日：2018-01-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Ryota HODO ,  Motomu KURATA ,  Shinya SASAGAWA ,  Satoru OKAMOTO ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  H01L29/786 ,  H01L23/532 ,  H01L21/463 ,  H01L21/467 ,  H01L29/66 ,  H01L21/02 ,  H01L23/522 ,  H01L21/768 ,  H01L29/778

CPC classification number: H01L27/1225 ,  H01L21/02565 ,  H01L21/463 ,  H01L21/467 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.

公开(公告)号：US20170236839A1

公开(公告)日：2017-08-17

申请号：US15420628

申请日：2017-01-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yuta ENDO ,  Kiyoshi KATO ,  Satoru OKAMOTO

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/768 ,  H01L27/105 ,  H01L23/528 ,  H01L23/532 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/1207 ,  H01L21/0206 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/8258 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first insulator; a transistor over the first insulator; a second insulator over the transistor; a first conductor embedded in an opening in the second insulator; a barrier layer over the first conductor; a third insulator over the second insulator and over the barrier layer; and a second conductor over the third insulator. The first insulator, the third insulator, and the barrier layer have a barrier property against oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor includes an oxide semiconductor. The barrier layer, the third insulator, and the second conductor function as a capacitor.

公开(公告)号：US20170207347A1

公开(公告)日：2017-07-20

申请号：US15408719

申请日：2017-01-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Hideomi SUZAWA ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Satoru OKAMOTO

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/146 ,  H01L29/49 ,  H01L27/12 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/78696 ,  H01L27/1225 ,  H01L27/14616 ,  H01L29/401 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78693 ,  H01L2029/42388

Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

公开(公告)号：US20160260822A1

公开(公告)日：2016-09-08

申请号：US15056356

申请日：2016-02-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoru OKAMOTO ,  Shinya SASAGAWA

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/24 ,  H01L29/40 ,  H01L29/78 ,  H01L29/22

CPC classification number: H01L29/66969 ,  H01L21/385 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/22 ,  H01L29/24 ,  H01L29/401 ,  H01L29/408 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/78 ,  H01L29/786 ,  H01L29/7869 ,  H01L29/78696

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.

Abstract translation: 提供一分钟晶体管。 提供具有低寄生电容的晶体管。 提供具有高频特性的晶体管。 提供包括晶体管的半导体器件。 半导体器件包括氧化物半导体，第一导体，第二导​​体，第三导体，第一绝缘体和第二绝缘体。 第一导体与氧化物半导体重叠，第一绝缘体位于它们之间。 第二绝缘体具有开口，并且第二绝缘体的侧表面与开口中的第一导体的侧表面重叠，其中第一绝缘体位于其间。 第二导体的表面的一部分和第三导体的表面的一部分与开口中的第一绝缘体接触。 氧化物半导体与第二导体和第三导体重叠。