公开(公告)号：US09859443B2

公开(公告)日：2018-01-02

申请号：US15362903

申请日：2016-11-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiromichi Godo ,  Yasuhiko Takemura

IPC: H01L29/78 ,  H01L29/786 ,  H01L27/06 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/12 ,  H01L49/02 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10826 ,  H01L27/10852 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L28/90 ,  H01L29/41733 ,  H01L29/785 ,  H01L29/78609

Abstract: Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface, a gate insulating film formed to cover the oxide semiconductor, and a gate electrode which is formed to cover the gate insulating film. The gate electrode partly overlaps a source electrode and a drain electrode. The source electrode and the drain electrode are in contact with at least a top surface of the oxide semiconductor. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate electrode, so that electrons injected from the source electrode or the drain electrode can be effectively removed, and most of the space between the source electrode and the drain electrode can be a depletion region; thus, off-state current can be reduced.

公开(公告)号：US09825042B2

公开(公告)日：2017-11-21

申请号：US15172183

申请日：2016-06-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuhiko Takemura

IPC: G11C11/24 ,  H01L27/108 ,  G11C8/14 ,  G11C11/404 ,  G11C11/4076 ,  G11C11/408 ,  H01L27/02 ,  H01L27/06 ,  H01L27/12 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4096 ,  H01L27/092 ,  G11C7/02 ,  G11C11/4097

CPC classification number: H01L27/10897 ,  G11C7/02 ,  G11C8/14 ,  G11C11/404 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10805 ,  H01L27/10811 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255

Abstract: In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m_1 or the like). Further, each cell includes selection transistors STr1_n_m and STr2_n_m and an amplifier circuit AMP_n_m that is a complementary inverter or the like is connected to the selection transistor STr2_n_m. Since parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential change due to electric charge in a capacitor of each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and can be output to the bit line.

公开(公告)号：US09704960B2

公开(公告)日：2017-07-11

申请号：US15216016

申请日：2016-07-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuhiko Takemura

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/08 ,  H01L29/788 ,  H01L27/105 ,  H01L27/108

CPC classification number: H01L29/0847 ,  H01L27/1052 ,  H01L27/10873 ,  H01L29/42324 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/788 ,  H01L29/7881

Abstract: A structure with which the zero current of a field effect transistor using a conductor-semiconductor junction can be reduced is provided. A floating electrode (102) including a conductor or a semiconductor and being enclosed by an insulator (104) is formed between a semiconductor layer (101) and a gate (105) so as to cross the semiconductor layer (101) and the floating electrode (102) is charged, whereby carriers are prevented from flowing from a source electrode (103a) or a drain electrode (103b). Accordingly, a sufficiently low carrier concentration can be kept in the semiconductor layer (101) and thus the zero current can be reduced.

公开(公告)号：US09704886B2

公开(公告)日：2017-07-11

申请号：US14272824

申请日：2014-05-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yasuhiko Takemura

IPC: H03K19/094 ,  H01L27/12 ,  H03K19/173

CPC classification number: H01L27/1225 ,  H03K19/1737

Abstract: A plurality of writing transistors are connected in series, and a gate of a pass transistor, an input terminal of an inverter, or the like is directly or indirectly connected to each connection portion of the writing transistors. For example, a signal processing device includes first to third pass transistors, one semiconductor layer, and first to third wirings that overlap with the semiconductor layer and do not overlap with each other. Potentials of the first to third wirings can each change conductivities of at least portions of the semiconductor layer that overlap with the respective wirings. Gates of the first to third pass transistors are electrically connected to the semiconductor layer and are brought into a floating state depending on the conductivities of the portions of the semiconductor layer. Conduction between sources and drains of the pass transistors is controlled by potentials of the gates in the floating state.

公开(公告)号：US09571099B2

公开(公告)日：2017-02-14

申请号：US15145967

申请日：2016-05-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuhiko Takemura

IPC: H03K19/00 ,  G11C11/412 ,  H01L27/11 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/0013 ,  G11C11/412 ,  H01L27/1104 ,  H03K19/1737 ,  H03K19/1776

Abstract: A method for driving a semiconductor device capable of reducing an area of a multiplexer and reducing its power consumption is provided. In a method for operating a semiconductor device including a memory and a multiplexer, a first transistor is connected to a first capacitor, and a second transistor is connected to a second capacitor. In the multiplexer, in a third transistor, a source is connected to a first input terminal and a drain is connected to an output terminal and, in a fourth transistor, a source is connected to a second input terminal and a drain is connected to the output terminal. Further, a step of holding a first potential in a node to which the first transistor, the first capacitor, and a gate of the third transistor are connected and holding a second potential higher than the first potential in the node is included.

Abstract translation: 提供一种用于驱动能够减少多路复用器的面积并降低其功耗的半导体器件的方法。 在用于操作包括存储器和多路复用器的半导体器件的方法中，第一晶体管连接到第一电容器，第二晶体管连接到第二电容器。 在多路复用器中，在第三晶体管中，源极连接到第一输入端子，漏极连接到输出端子，在第四晶体管中，源极连接到第二输入端子，漏极连接到 输出端子。 此外，包括在第一晶体管，第一电容器和第三晶体管的栅极连接并保持比节点中的第一电位高的第二电位的节点中保持第一电位的步骤。

公开(公告)号：US09443990B2

公开(公告)日：2016-09-13

申请号：US14464966

申请日：2014-08-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Yasuhiko Takemura ,  Tetsuhiro Tanaka ,  Takayuki Inoue ,  Toshihiko Takeuchi ,  Yasumasa Yamane ,  Shunpei Yamazaki

IPC: H03K19/003 ,  H01L21/324 ,  H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  G11C16/04 ,  H01L27/12 ,  H03K19/00 ,  H03K19/177

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/1225 ,  H01L29/4234 ,  H01L29/66833 ,  H03K19/0013 ,  H03K19/17736

Abstract: A manufacturing method of a semiconductor device in which the threshold is adjusted is provided. In a semiconductor device including a plurality of transistors arranged in a matrix each including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer between the gate electrode and the semiconductor, electrons are trapped in the charge trap layer by performing heat treatment and, simultaneously, keeping a potential of the gate electrode higher than that of the source or drain electrode for 1 second or more. By this process, the threshold increases and Icut decreases. A circuit that supplies a signal to the gate electrode (e.g., word line driver) is provided with a selection circuit formed of an OR gate, an XOR gate, or the like, whereby potentials of word lines can be simultaneously set higher than potentials of bit lines.

Abstract translation: 提供了其中调整阈值的半导体器件的制造方法。 在包括以矩阵形式排列的多个晶体管的半导体器件中，每个晶体管包括半导体，与该半导体电连接的源极或漏极，栅电极和栅电极与半导体之间的电荷陷阱层，电子被俘获在 通过进行热处理，同时使栅电极的电位比源极或漏极的电位高1秒以上。 通过该过程，阈值增加并且Icut减小。 向门电极（例如字线驱动器）提供信号的电路设置有由或门，异或门等形成的选择电路，由此可以将字线的电位同时设置为高于电位 位线。

公开(公告)号：US09368059B2

公开(公告)日：2016-06-14

申请号：US14188029

申请日：2014-02-24

Applicant: Semiconductor Energy Laboratory Co. Ltd.

Inventor： Yasuhiko Takemura

IPC: G09G3/32 ,  G06F3/041 ,  G06F3/042

CPC classification number: G06F3/0412 ,  G06F3/0421 ,  G06F3/044 ,  G06F3/046 ,  G09G3/2092 ,  G09G3/32

Abstract: A semiconductor device having a novel data input and output panel with high definition is provided. A method for driving the semiconductor device having the novel data input and output panel with high definition is provided. The data input and output panel includes, over a substrate, proximity sensors, signal lines electrically connected to the proximity sensors, and pixels electrically connected to the signal lines. The signal lines can supply image signals to the pixels, can supply control signals to the proximity sensors, and can be supplied with sensing signals from the proximity sensors.

Abstract translation: 提供具有高分辨率的新型数据输入和输出面板的半导体器件。 提供一种驱动具有高分辨率的新型数据输入和输出面板的半导体器件的方法。 数据输入和输出面板包括在衬底上的接近传感器，电连接到接近传感器的信号线以及电连接到信号线的像素。 信号线可以向像素提供图像信号，可以向接近传感器提供控制信号，并且可以从接近传感器提供感测信号。

公开(公告)号：US09337345B2

公开(公告)日：2016-05-10

申请号：US14336118

申请日：2014-07-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yasuhiko Takemura

IPC: G11C11/00 ,  H01L29/786 ,  H01L21/84 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L49/02 ,  G11C5/10 ,  G11C11/401

CPC classification number: H01L27/10808 ,  G11C5/10 ,  G11C11/401 ,  G11C11/4085 ,  H01L21/84 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0688 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10897 ,  H01L27/1207 ,  H01L28/91 ,  H01L29/7869

Abstract: The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.

Abstract translation: DRAM的存储器容量增强。 半导体存储器件包括：驱动器电路，其包括单晶半导体衬底的一部分，设置在驱动电路上的多层布线层;以及设置在多层布线层上的存储单元阵列层。 也就是说，存储单元阵列与驱动电路重叠。 因此，与在含有单晶体半导体材料的基板的同一平面上设置驱动电路和存储单元阵列的情况相比，可以提高半导体存储器件的集成度。

公开(公告)号：US09257432B2

公开(公告)日：2016-02-09

申请号：US14617312

申请日：2015-02-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuhiko Takemura

IPC: H01L27/108 ,  H01L27/115

CPC classification number: H01L27/108 ,  H01L27/10844 ,  H01L27/1156

Abstract: A highly integrated gain cell-type semiconductor memory is provided. A first insulator, a read bit line, a second insulator, a third insulator, a first semiconductor film, first conductive layers, and the like are formed. A projecting insulator is formed thereover. Then, second semiconductor films and a second gate insulating film are formed to cover the projecting insulator. After that, a conductive film is formed and subjected to anisotropic etching, so that write word lines are formed on side surfaces of the projecting insulator. A third contact plug for connection to a write bit line is formed over a top of the projecting insulator. With such a structure, the area of the memory cell can be 4F2 at a minimum.

Abstract translation: 提供高度集成的增益单元型半导体存储器。 形成第一绝缘体，读位线，第二绝缘体，第三绝缘体，第一半导体膜，第一导电层等。 在其上形成突出的绝缘体。 然后，形成第二半导体膜和第二栅极绝缘膜以覆盖突出的绝缘体。 之后，形成导电膜并进行各向异性蚀刻，使得写入字线形成在突出绝缘体的侧表面上。 用于连接到写位线的第三接触插塞形成在突出绝缘体的顶部上。 利用这种结构，存储单元的面积最小可以是4F2。

公开(公告)号：US09230615B2

公开(公告)日：2016-01-05

申请号：US13655077

申请日：2012-10-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuhiko Takemura

IPC: G11C7/08 ,  G11C7/02 ,  G11C11/4091 ,  G11C11/4094

CPC classification number: G11C7/02 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4094

Abstract: In a conventional DRAM, data read errors are more likely to occur along with miniaturization of DRAM A small change in the potential of a first bit line is inverted by a first inverter constituted by an n-channel transistor and a p-channel transistor, and is output to a second bit line through a first selection transistor, which is a first switch. Since the potential of the second bit line is the inverse of the potential of the first bit line, the potential difference between the first bit line and the second bit line is increased. The increased potential difference is amplified by a known sense amplifier, a flip-flop circuit composed of the first inverter and a second inverter (constituted by an n-channel transistor and a p-channel transistor), or the like.

Abstract translation: 在常规DRAM中，随着DRAM的小型化，更可能发生数据读取错误。第一位线的电位的小的变化由由n沟道晶体管和p沟道晶体管构成的第一反相器反相，以及 通过作为第一开关的第一选择晶体管输出到第二位线。 由于第二位线的电位是第一位线的电位的倒数，所以第一位线和第二位线之间的电位差增大。 增加的电位差​​由已知的读出放大器，由第一反相器和第二反相器（由n沟道晶体管和p沟道晶体管构成）构成的触发电路等放大。