公开(公告)号：US11736098B2

公开(公告)日：2023-08-22

申请号：US17866517

申请日：2022-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Youngmin Jo ,  Chiweon Yoon ,  Byungkwan Chun ,  Byunghoon Jeong

IPC: H03K5/14 ,  H03L7/081 ,  H03K5/135 ,  H03K5/00

CPC classification number: H03K5/14 ,  H03K5/135 ,  H03L7/0816 ,  H03K2005/00247

Abstract: A memory package includes a plurality of memory chips, and an interface chip relaying communications between a controller and the plurality of memory chips and receiving a plurality of signals from the plurality of memory chips. The interface chip includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.

公开(公告)号：US11714579B2

公开(公告)日：2023-08-01

申请号：US17828176

申请日：2022-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonkyoo Lee ,  Jeongdon Ihm ,  Chiweon Yoon ,  Byunghoon Jeong

IPC: G06F3/06 ,  G06F1/06 ,  G06F13/16 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F3/0659 ,  G06F1/06 ,  G06F3/0613 ,  G06F3/0679 ,  G06F13/1668 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

公开(公告)号：US20230170030A1

公开(公告)日：2023-06-01

申请号：US18160620

申请日：2023-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung KIM ,  Youngmin Jo ,  Chiweon Yoon

IPC: G11C16/32

CPC classification number: G11C16/32 ,  G11C16/0483

Abstract: A nonvolatile memory device includes a first memory chip and a second memory chip connected to a controller through the same channel. The first memory chip generates a first signal from a first internal clock signal based on a clock signal received from the controller. The second memory chip generates a second signal from a second internal clock signal based on the clock signal, and performs a phase calibration operation on the second signal on the basis of a phase of the first signal by delaying the second internal clock signal based on a phase difference between the first and second signals.

公开(公告)号：US11282851B2

公开(公告)日：2022-03-22

申请号：US16662073

申请日：2019-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Chanho Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Chiweon Yoon

IPC: H01L27/11573 ,  H01L23/522 ,  H01L27/1157 ,  H01L29/78 ,  H01L29/94 ,  H01L27/11582

Abstract: A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.

公开(公告)号：US10121542B2

公开(公告)日：2018-11-06

申请号：US15681479

申请日：2017-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan Nam ,  Daeseok Byeon ,  Chiweon Yoon

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C16/26 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder circuit. The row decoder circuit turns on memory cells of a plurality of cell strings of a selected memory block after applying a first prepulse to a first dummy word line connected to first dummy memory cells after applying a second prepulse to a second dummy word line connected to second dummy memory cells.

公开(公告)号：US10102910B2

公开(公告)日：2018-10-16

申请号：US15806543

申请日：2017-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Sang Lee ,  Donghun Kwak ,  Daeseok Byeon ,  Chiweon Yoon

IPC: G11C11/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/24 ,  G11C16/04 ,  G11C16/26

Abstract: A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.

公开(公告)号：US09496038B1

公开(公告)日：2016-11-15

申请号：US15091843

申请日：2016-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Kwak ,  Sang-Wan Nam ,  Daeseok Byeon ,  Chiweon Yoon

IPC: G11C16/04 ,  G11C16/28 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C7/14 ,  G11C8/14 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3418

Abstract: A three-dimensional flash memory device includes a plurality of cell strings arranged in a direction perpendicular to a substrate. The three-dimensional flash memory includes a first dummy word line disposed between a ground selection line and a main word line, and a second dummy word line disposed between the main word line and a string selection line and being asymmetric with respect to the first dummy word line. Voltages of different levels are respectively applied to the first and second dummy word lines during a read operation.

Abstract translation: 三维闪速存储器件包括沿垂直于衬底的方向布置的多个单元串。 三维闪存包括设置在地选择线和主字线之间的第一虚拟字线和设置在主字线和字串选择线之间的第二虚拟字线，并且相对于第一伪线不对称 字线。 在读取操作期间，不同电平的电压分别应用于第一和第二伪字线。