公开(公告)号：US20250107098A1

公开(公告)日：2025-03-27

申请号：US18807157

申请日：2024-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Jae-Bok Baek ,  Donghyuck Jang ,  Jeehoon Han

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: Disclosed are semiconductor devices and electronic systems. The semiconductor device comprises a semiconductor substrate including first and second cell array regions and a connection region including a lower pad region and an upper pad region, a peripheral circuit structure including peripheral circuits on the semiconductor substrate, and a cell array structure on the peripheral circuit structure and including a first stack structure including first conductive patterns stacked on the peripheral circuit structure and a second stack structure including second conductive patterns stacked on the first stack structure. The first stack structure includes a connection portion that has a uniform thickness on the upper pad region, and first and second stepwise structures that are asymmetric with each other on the lower pad region. The second stack structure includes third and fourth stepwise structures that are symmetric with each other on the connection portion of the first stack structure.

公开(公告)号：US20250056807A1

公开(公告)日：2025-02-13

申请号：US18790129

申请日：2024-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juseong Min ,  Jaebok Baek ,  Taekkyu Yoon ,  Jeehoon Han

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device includes a substrate, active regions extending on the substrate in a first direction, the active regions spaced apart from each other in a second direction perpendicular to the first direction, and arranged in a third direction oblique to the first direction and second direction, and gate electrodes disposed on the active regions and including a first edge extending in the second direction, a second edge extending in the first direction, and a corner region defined by the first edge and the second edge, wherein the corner region includes a protrusion having a width narrowing in a direction away from a center of each of the gate electrodes in plan view.

公开(公告)号：US12185548B2

公开(公告)日：2024-12-31

申请号：US17318306

申请日：2021-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Giyong Chung ,  Jaeryong Sim ,  Kwangyoung Jung ,  Jeehoon Han

IPC: H10B43/50 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B41/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a memory cell region. The memory cell region includes a memory stack structure including a first stack structure and a second stack structure; a plurality of channel structures vertically penetrating through the memory stack structure and connected to the second substrate; at least one first dummy structure; and at least one second dummy structure. At least a portion of the first dummy structure does not overlap the second dummy structure in a vertical direction.

公开(公告)号：US12185543B2

公开(公告)日：2024-12-31

申请号：US17742043

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghun Chun ,  Kwangyoung Jung ,  Youngji Noh ,  Junghwan Park ,  Jeehoon Han

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, separation regions penetrating the gate electrodes, extending in the first direction and a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, and crack prevention layers disposed on at least a portion of the separation regions, wherein each of the separation regions includes a lower region and upper regions spaced apart from each other in the second direction on the lower region and protruding upwardly from the lower region, and wherein the crack prevention layers are in contact with upper surfaces of the upper regions.

公开(公告)号：US20240422983A1

公开(公告)日：2024-12-19

申请号：US18404198

申请日：2024-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Seo-Goo Kang ,  Seunghyun Lee ,  Jeehoon Han

IPC: H10B43/35 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device and an electronic system are provided. The semiconductor device may include a substrate including a cell array region and a connection region, a stacked structure including conductive patterns stacked on the substrate, an inner supporter that extends into the stacked structure in the connection region, a contact plug that extends into a portion of the stacked structure and electrically connected to one of the conductive patterns and at least partially extends around the inner supporter in plan view, an insulating spacer between the contact plug and the stacked structure and at least partially extends around the contact plug, and outer supporters spaced apart from the contact plug in the connection region and extending into the stacked structure.

公开(公告)号：US20240292613A1

公开(公告)日：2024-08-29

申请号：US18586624

申请日：2024-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Jeehoon Han

IPC: H10B43/20 ,  H01L29/04 ,  H01L29/06

CPC classification number: H10B43/20 ,  H01L29/045 ,  H01L29/0696

Abstract: A three-dimensional nonvolatile memory device includes: a plurality of insulating layers stacked on a substrate in a vertical direction substantially perpendicular to a surface of the substrate; a plurality of channel layers positioned between the plurality of insulating layers, and elongated in a first horizontal direction that is parallel to the surface of the substrate, wherein the plurality of channel layers includes a first metal element; a diffusion stop layer conformally formed in a trench passing through the plurality of insulating layers and the plurality of channel layers in the vertical direction; and a crystalline semiconductor pattern between each of the plurality of channel layers and the diffusion stop layer, wherein the crystalline semiconductor pattern includes a second metal element, wherein a concentration of the second metal element in the crystalline semiconductor pattern is higher than a concentration of the first metal element in the plurality of channel layers.

公开(公告)号：US12058866B2

公开(公告)日：2024-08-06

申请号：US17204248

申请日：2021-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeryong Sim ,  Shinhwan Kang ,  Jeehoon Han

IPC: H01L29/76 ,  H01L23/48 ,  H01L29/94 ,  H01L31/062 ,  H10B43/27 ,  H10B43/50

CPC classification number: H10B43/50 ,  H01L23/481 ,  H10B43/27

Abstract: A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy vertical structure are contacting the pattern structure, and wherein at least one of the dummy vertical structures extend further into the pattern structure than the memory vertical structure in a downward direction.

公开(公告)号：US20240162225A1

公开(公告)日：2024-05-16

申请号：US18318854

申请日：2023-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juseong MIN ,  Jae-Bok Baek ,  Taekkyu Yoon ,  Seungwook Choi ,  Jeehoon Han ,  Taeyoon Hong

IPC: H01L27/08 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L27/0802 ,  H01L21/30604 ,  H01L21/308 ,  H01L28/20

Abstract: A semiconductor device includes an active pattern having sharp corners. The semiconductor device includes a peripheral circuit including a substrate, a resistor device in the substrate, and an active pattern on the substrate. When viewed in a plan view, the active pattern includes corners in a serpentine shape, and first and second shapes of the corners are different from each other.

公开(公告)号：US11925020B2

公开(公告)日：2024-03-05

申请号：US17473006

申请日：2021-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan Kang ,  Younghwan Son ,  Haemin Lee ,  Kohji Kanamori ,  Jeehoon Han

IPC: H10B43/00 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

公开(公告)号：US11844214B2

公开(公告)日：2023-12-12

申请号：US17362903

申请日：2021-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeryong Sim ,  Giyong Chung ,  Dongsik Oh ,  Jeehoon Han

IPC: H10B41/41 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H01L29/423 ,  H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B41/41 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate that includes a first active region, a second active region, and an isolation region. An isolation layer pattern fills a trench in the substrate. A first gate insulation layer pattern and a first gate electrode structure are formed on the first active region. A second gate insulation layer pattern and second gate electrode structure are formed on the second active region. The first gate electrode structure includes a first polysilicon pattern, a second polysilicon pattern, and a first metal pattern. The second gate electrode structure includes a third polysilicon pattern, a fourth polysilicon pattern, and a second metal pattern. An upper surface of the isolation layer pattern is higher than upper surfaces of each of the first and third polysilicon patterns. A sidewall of each of the first and third polysilicon patterns contacts sidewalls of the isolation layer pattern.