公开(公告)号：US11889694B2

公开(公告)日：2024-01-30

申请号：US17397846

申请日：2021-08-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Zhixin Cui ,  Rajdeep Gautam ,  Hiroyuki Ogawa

IPC: G11C11/34 ,  H10B43/27 ,  G11C5/06 ,  H01L23/522 ,  G11C8/14 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35

CPC classification number: H10B43/27 ,  G11C5/063 ,  G11C8/14 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/35

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

公开(公告)号：US20230328981A1

公开(公告)日：2023-10-12

申请号：US17715662

申请日：2022-04-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nobuyuki Fujimura ,  Shunsuke Takuma ,  Takashi Kudo ,  Satoshi Shimizu ,  Zhixin Cui

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, a memory opening vertically extending through the first alternating stack and having a tapered sidewall surface at a level of one of the first electrically conductive layers, and a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel. One of the first electrically conductive layers includes a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening and has a contoured sidewall having a tapered sidewall segment that is parallel to the tapered sidewall surface of the lateral protrusion.

公开(公告)号：US11342245B2

公开(公告)日：2022-05-24

申请号：US16921146

申请日：2020-07-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Hirofumi Tokita

IPC: H01L23/48 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11556

Abstract: A first-tier structure includes a first vertically alternating sequence of first continuous insulating layers and first continuous sacrificial material layers and a first-tier retro-stepped dielectric material portion overlying first stepped surfaces of the first vertically alternating sequence. A second vertically alternating sequence of second continuous insulating layers and second continuous sacrificial material layers is formed over the first-tier structure. Retro-stepped dielectric material portions are formed in each of the first-tier structure and the second-tier structure. After formation of memory stack structures, electrically conductive layers replace portions of the first and second continuous sacrificial material layers. Laterally-isolated contact via structures can be formed through the second-tier structure and a first-tier retro-stepped dielectric material portion on first electrically conductive layers in the first-tier structure. Sacrificial landing pad structures can be employed to enable concurrent formation of contact via cavities through the retro-stepped dielectric material portions.

公开(公告)号：US11335671B2

公开(公告)日：2022-05-17

申请号：US16886164

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Zhixin Cui ,  Rajdeep Gautam

IPC: H01L25/18 ,  H01L23/00 ,  G11C7/12 ,  H01L25/00 ,  G11C7/06

Abstract: Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.

公开(公告)号：US11069410B1

公开(公告)日：2021-07-20

申请号：US16985335

申请日：2020-08-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Hardwell Chibvongodze ,  Rajdeep Gautam

IPC: G11C16/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11597 ,  G11C17/16 ,  G11C17/18 ,  G11C16/04 ,  G11C16/26 ,  G11C11/22 ,  H01L27/112

Abstract: First alternating stacks of first insulating strips and first spacer material strips is formed in a first device region, second alternating stacks of second insulating strips and second spacer material strips are formed in a second device region. Each of the first line trenches is filled with a respective laterally alternating sequence of memory stack structures and first dielectric pillar structures to form a three-dimensional NAND memory. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements. Each of the second line trenches with a respective laterally alternating sequence of active region assemblies of lateral field effect transistors and second dielectric pillar structures to form a three-dimensional NOR memory. Each of the active region assemblies includes a source pillar, a drain pillar, and a tubular channel region. The spacer material strips include, or are subsequently replaced with, electrically conductive strips.

公开(公告)号：US11049876B2

公开(公告)日：2021-06-29

申请号：US16881353

申请日：2020-05-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Michimoto Kaminaga ,  Zhixin Cui

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L21/768 ,  H01L27/11556 ,  H01L23/532 ,  H01L23/522 ,  H01L27/11575 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526

Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-insulated structure includes a conductive via structure having an upper conductive via portion overlying and contacting an annular area of a top surface of one of the electrically conductive layers, a lower conductive via portion having a lesser lateral dimension than the upper conductive via portion and extending through at least a bottommost one of the electrically conductive layers, and an interconnection conductive via portion located between the upper conductive via portion and the lower conductive via portion and contacting a cylindrical sidewall of the one of the electrically conductive layers.

公开(公告)号：US10903222B2

公开(公告)日：2021-01-26

申请号：US16408722

申请日：2019-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Masaaki Higashitani ,  Masanori Tsutsumi ,  Zhixin Cui

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/535 ,  H01L21/285 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: A three-dimensional memory device includes source-level material layers located over a substrate and including a lower semiconductor layer, a source contact layer, and an upper semiconductor layer. The lower semiconductor layer includes a first boron-doped semiconductor material, the upper semiconductor layer includes carbon doped second boron-doped semiconductor material, and the source contact layer includes a boron-doped semiconductor material. An alternating stack of insulating layers and electrically conductive layers is located over the source-level material layers. Memory stack structures vertically extend through the alternating stack, the upper semiconductor layer, and the source contact layer. Each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel that contacts the source contact layer. Carbon atoms in the upper semiconductor layer and optionally the lower semiconductor layer suppress diffusion of boron atoms into the vertical semiconductor channel.

公开(公告)号：US10818542B2

公开(公告)日：2020-10-27

申请号：US16362895

申请日：2019-03-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Fei Zhou ,  Raghuveer S. Makala

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/11565 ,  H01L27/11519

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.

公开(公告)号：US10756106B2

公开(公告)日：2020-08-25

申请号：US16202713

申请日：2018-11-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Michiaki Sano ,  Ken Oowada ,  Zhixin Cui

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/8234 ,  H01L27/11524 ,  H01L27/1157

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing word lines and drain select gate electrodes located over a substrate, and memory stack structures containing a respective vertical semiconductor channel and a memory film including a tunneling dielectric and a charge storage layer. A first portion of a first charge storage layer located in a first memory stack structure at level of a first drain select gate electrode is thicker than a first portion of a second charge storage layer located in a second memory stack structure at the level of the first drain select electrode.

公开(公告)号：US10741579B2

公开(公告)日：2020-08-11

申请号：US16215912

申请日：2018-12-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Masatoshi Nishikawa ,  Ken Oowada

IPC: H01L27/11582 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L23/528 ,  H01L21/311 ,  H01L21/762 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/265 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/36 ,  H01L21/306

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.