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    Floating body field-effect transistors, and methods of forming floating body field-effect transistors
    41.
    发明授权
    Floating body field-effect transistors, and methods of forming floating body field-effect transistors 有权
    浮体场效应晶体管，以及形成浮体场效应晶体管的方法

    公开(公告)号：US07948008B2

    公开(公告)日：2011-05-24

    申请号：US11925573

    申请日：2007-10-26

    申请人： Jun Liu ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch ,  Di Li

    发明人： Jun Liu ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch ,  Di Li

    IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392

    CPC分类号： H01L27/1203 ,  H01L27/10802 ,  H01L29/66477 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

    摘要翻译： 在一个实施例中，浮体场效应晶体管包括一对在其间容纳浮体通道区的源/漏区。 源极/漏极区域和浮体沟道区域被接纳在绝缘体上。 栅电极靠近浮体通道区域。 门电介质被接收在栅电极和浮体沟道区之间。 浮体通道区域具有半导体SixGe（1-x）区域。 浮体通道区域具有容纳在半导体SixGe（1-x）区域和栅极电介质之间的半导体硅包覆区域。 半导体SixGe（1-x）含量区域在含半导体硅的区域内具有比任何Ge量更大的Ge量。 考虑了其他实施例，包括形成浮体场效应晶体管的方法。

    3D MEMORY DEVICES DECODING AND ROUTING SYSTEMS AND METHODS
    42.
    发明申请
    3D MEMORY DEVICES DECODING AND ROUTING SYSTEMS AND METHODS 有权
    3D存储器件解码和路由系统和方法

    公开(公告)号：US20110051512A1

    公开(公告)日：2011-03-03

    申请号：US12547337

    申请日：2009-08-25

    申请人： Michael P. Violette

    发明人： Michael P. Violette

    IPC分类号： G11C16/04 ,  G11C5/02 ,  G11C8/00

    CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C5/063 ,  G11C8/10 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    摘要： 3D memory devices are disclosed, such as those that include multiple two-dimensional tiers of memory cells. Each tier may be fully or partially formed over a previous tier to form a memory device having two or more tiers. Each tier may include strings of memory cells where each of the strings are coupled between a source select gate and a drain select gate such that each tier is decoded using the source/drain select gates. Additionally, the device can include a wordline decoder for each tier that is only coupled to the wordlines for that tier.

    摘要翻译： 公开了3D存储器件，例如包括多个二维存储器单元的那些器件。 每个层可以在先前层上完全或部分地形成，以形成具有两层或多层的存储器件。 每个层可以包括存储器单元串，其中每个串耦合在源极选择栅极和漏极选择栅极之间，使得使用源极/漏极选择栅极对每个层进行解码。 此外，该设备可以包括仅耦合到该层的字线的每个层的字线解码器。

    Phase change memory cell with constriction structure
    44.
    发明授权
    Phase change memory cell with constriction structure 有权
    具有收缩结构的相变记忆体

    公开(公告)号：US07852658B2

    公开(公告)日：2010-12-14

    申请号：US12049056

    申请日：2008-03-14

    申请人： Jun Liu ,  Michael P. Violette

    发明人： Jun Liu ,  Michael P. Violette

    IPC分类号： G11C11/00

    CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1675 ,  H01L45/1683

    摘要： Some embodiments include apparatus and methods having a memory cell with a first electrode and a second electrode, and a memory element directly contacting the first and second electrodes. The memory element may include a programmable portion having a material configured to change between multiple phases. The programmable portion may be isolated from the first electrode by a first portion of the memory element and isolated from the second electrode by a second portion of the memory element.

    摘要翻译： 一些实施例包括具有具有第一电极和第二电极的存储单元的设备和方法，以及直接接触第一和第二电极的存储元件。 存储元件可以包括具有被配置为在多个相之间变化的材料的可编程部分。 可编程部分可以通过存储元件的第一部分与第一电极隔离，并且通过存储元件的第二部分与第二电极隔离。

    Local interconnect structure for integrated circuit devices, source structure for the same, and method for fabricating the same
    46.
    发明授权
    Local interconnect structure for integrated circuit devices, source structure for the same, and method for fabricating the same 失效
    用于集成电路器件的局部互连结构，用于其的源结构及其制造方法

    公开(公告)号：US06844601B2

    公开(公告)日：2005-01-18

    申请号：US10000479

    申请日：2001-10-24

    申请人： Jigish D. Trivedi ,  Michael P. Violette

    发明人： Jigish D. Trivedi ,  Michael P. Violette

    IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L29/76 ,  H01L23/48 ,  H01L29/94

    CPC分类号： H01L21/76895 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A process for making a local interconnect and the structures formed thereby. The process is practiced by forming a Ti layer having a nitrogen-rich upper portion over a portion of a substrate, forming a refractory metal layer on the Ti layer, forming a Si layer on the refractory metal layer, removing a portion of the Si layer, and heating to form a local interconnect structure. During this process, a source structure for the local interconnect is formed. This source structure comprises a Ti layer having a nitrogen-rich upper portion overlying a portion of a substrate, a refractory metal layer overlying the Ti layer, and a silicon layer overlying the refractory metal layer. The resulting local interconnect comprises a titanium silicide layer disposed on a portion of a substrate, a nitrogen-rich Ti layer disposed on the titanium silicide layer, and a refractory metal silicide layer disposed on the nitrogen-rich Ti layer. The local interconnect is especially useful for reducing cratering and consumption of silicon regions underlying the local interconnect.

    摘要翻译： 一种制造局部​​互连的方法及由此形成的结构。 该方法通过在衬底的一部分上形成富含氮的上部的Ti层，在Ti层上形成难熔金属层，在难熔金属层上形成Si层，除去Si层的一部分 并加热以形成局部互连结构。 在该过程中，形成用于局部互连的源结构。 该源结构包括具有覆盖在衬底的一部分上的富氮上部的Ti层，覆盖在Ti层上的难熔金属层和覆盖在难熔金属层上的硅层。 得到的局部互连包括设置在衬底的一部分上的硅化钛层，设置在硅化钛层上的富氮Ti层和设置在富氮Ti层上的难熔金属硅化物层。 局部互连特别适用于减少局部互连底层硅片的凹坑和消耗。

    Method and apparatus for isolating a SRAM cell
    47.
    发明授权
    Method and apparatus for isolating a SRAM cell 失效
    用于隔离SRAM单元的方法和装置

    公开(公告)号：US06750107B1

    公开(公告)日：2004-06-15

    申请号：US09565429

    申请日：2000-05-05

    申请人： Michael P. Violette

    发明人： Michael P. Violette

    IPC分类号： H01L2176

    CPC分类号： H01L21/76202

    摘要： A static random access memory cell comprising a first inverter including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second inverter including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first inverter being cross-coupled with the second inverter, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first inverter; a second access transistor having an active terminal connected to the second inverter; and an isolator isolating the first pullup transistor from the second pullup transistor.

    摘要翻译： 一种静态随机存取存储单元，包括：第一反相器，包括第一p沟道上拉晶体管和与第一p沟道上拉晶体管串联的第一n沟道下拉晶体管; 第二反相器，包括第二p沟道上拉晶体管和与第二n沟道上拉晶体管串联的第二n沟道下拉晶体管，第一反相器与第二反相器交叉耦合，第一和第二上拉晶体管共享 一个共同的活跃区域; 第一存取晶体管，其具有连接到第一反相器的有源端子; 第二存取晶体管，具有连接到第二反相器的有源端子; 以及将第一上拉晶体管与第二上拉晶体管隔离的隔离器。

    Twin well methods of forming CMOS integrated circuitry
    48.
    发明授权
    Twin well methods of forming CMOS integrated circuitry 有权
    双阱形成CMOS集成电路的方法

    公开(公告)号：US06548383B1

    公开(公告)日：2003-04-15

    申请号：US09441912

    申请日：1999-11-17

    申请人： Jigish D. Trivedi ,  Zhongze Wang ,  Michael P. Violette

    发明人： Jigish D. Trivedi ,  Zhongze Wang ,  Michael P. Violette

    IPC分类号： H01L21425

    CPC分类号： H01L21/823892

    摘要： In accordance with an aspect of the invention, a twin-well method of forming CMOS integrated circuitry having first and second conductivity type gates includes conducting a first conductivity type well implant, a second conductivity type well implant, a first conductivity type gate implant and a second conductivity type gate implant using no more than two masking steps. In another aspect of the invention, a twin well method of forming CMOS integrated circuitry having first and second conductivity type transistor gates includes conducting a first conductivity type well implant and a second conductivity type gate implant in a common masking step.

    摘要翻译： 根据本发明的一个方面，形成具有第一和第二导电类型栅极的CMOS集成电路的双阱方法包括：导电第一导电类型阱注入，第二导电类型阱注入，第一导电型栅极注入和 使用不超过两个掩模步骤的第二导电类型栅极注入。 在本发明的另一方面，形成具有第一和第二导电类型晶体管栅极的CMOS集成电路的双阱法包括在公共掩模步骤中传导第一导电类型阱注入和第二导电类型栅极注入。

    Methods of forming a local interconnect method of fabricating integrated circuitry comprising an SRAM cell having a local interconnect and having circuitry peripheral to the SRAM cell and method of forming contact plugs
    49.
    发明授权
    Methods of forming a local interconnect method of fabricating integrated circuitry comprising an SRAM cell having a local interconnect and having circuitry peripheral to the SRAM cell and method of forming contact plugs 失效
    形成集成电路的局部互连方法的方法，该集成电路包括具有局部互连并且具有SRAM单元的外围电路的SRAM单元和形成接触插塞的方法

    公开(公告)号：US06333254B1

    公开(公告)日：2001-12-25

    申请号：US09737919

    申请日：2000-12-14

    申请人： Todd R. Abbott ,  Michael P. Violette ,  Charles H. Dennison

    发明人： Todd R. Abbott ,  Michael P. Violette ,  Charles H. Dennison

    IPC分类号： H01L214763

    CPC分类号： H01L27/11 ,  H01L21/76877 ,  H01L21/76895 ,  H01L27/1104

    摘要： In one implementation, a substrate is provided which has at least two nodes to be electrically connected. A first conductivity type semiconductive material is formed over and in electrical connection with one of the nodes. A conductive diffusion barrier material is formed over and in electrical connection with the first conductivity type semiconductive material. A second conductivity type semiconductive material is formed over and in electrical connection with the first conductivity type semiconductive material through the conductive diffusion barrier material, and over and in electrical connection with another of the nodes. The first conductivity type semiconductive material, the conductive diffusion barrier material and the second conductivity type semiconductive material are formed into a local interconnect electrically connecting the one node and the another node. Local interconnects fabricated by this and other methods are also contemplated. The invention includes in one implementation a method of forming contact plugs.

    摘要翻译： 在一个实施方案中，提供了具有至少两个要电连接的节点的基板。 第一导电类型的半导体材料形成在节点之一上并与其中的一个节点电连接。 导电扩散阻挡材料形成在第一导电类型半导体材料之上并与第一导电类型的半导体材料电连接。 第二导电类型半导体材料通过导电扩散阻挡材料形成在第一导电类型半导体材料之上并与电连接，并且与另一节点电连接。 第一导电型半导体材料，导电扩散阻挡材料和第二导电类型半导体材料形成为电连接一个节点和另一个节点的局部互连。 也可以设想通过该方法和其它方法制造的局部互连。 本发明在一个实施方案中包括形成接触塞的方法。

    Method of forming guard ringed schottky diode
    50.
    发明授权
    Method of forming guard ringed schottky diode 失效
    形成保护环肖特基二极管的方法

    公开(公告)号：US5696025A

    公开(公告)日：1997-12-09

    申请号：US597479

    申请日：1996-02-02

    申请人： Michael P. Violette ,  Fernando Gonzalez

    发明人： Michael P. Violette ,  Fernando Gonzalez

    IPC分类号： H01L21/329 ,  H01L21/28

    CPC分类号： H01L29/66143

    摘要： A method of forming a guard ring for a Schottky diode is comprised of the steps of forming anode and cathode contact openings. A layer of doped material is deposited and etched to create spacers in the anode and cathode openings. The outdiffusion of dopant from the spacers is controlled to form a guard ring in the well without affecting the active area. The method can be used to create a p-type guard ring in an n-well or an n-type guard ring in a p-well. A Schottky diode constructed according to the method is also disclosed.

    摘要翻译： 形成用于肖特基二极管的保护环的方法包括形成阳极和阴极接触开口的步骤。 沉积和蚀刻掺杂材料层，以在阳极和阴极开口中产生间隔物。 控制来自间隔物的掺杂剂的向外扩散，以在阱中形成保护环而不影响有效面积。 该方法可用于在p阱中的n阱或n型保护环中产生p型保护环。 还公开了根据该方法构造的肖特基二极管。