Semiconductor device with a dynamic gate-drain capacitance
    41.
    发明授权
    Semiconductor device with a dynamic gate-drain capacitance 有权
    具有动态栅极 - 漏极电容的半导体器件

    公开(公告)号:US07982253B2

    公开(公告)日:2011-07-19

    申请号:US12184819

    申请日:2008-08-01

    IPC分类号: H01L29/94

    摘要: A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.

    摘要翻译: 具有动态栅极漏极电容的半导体器件。 一个实施例提供一种半导体器件。 该器件包括半导体衬底,场效应晶体管结构,其包括源区,第一体区,漏区,栅电极结构和栅极绝缘层。 栅极绝缘层设置在栅电极结构和体区之间。 栅极电极结构和漏极区域部分地形成电容器结构,其包括栅极 - 漏极电容,该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地改变。 栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值,或者在给定的反向电压下包括平台状过程。

    SEMICONDUCTOR DEVICE WITH A DYNAMIC GATE-DRAIN CAPACITANCE
    44.
    发明申请
    SEMICONDUCTOR DEVICE WITH A DYNAMIC GATE-DRAIN CAPACITANCE 有权
    具有动态栅极导通电容的半导体器件

    公开(公告)号:US20100025748A1

    公开(公告)日:2010-02-04

    申请号:US12184819

    申请日:2008-08-01

    IPC分类号: H01L29/94 H01L21/8234

    摘要: A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.

    摘要翻译: 具有动态栅极漏极电容的半导体器件。 一个实施例提供一种半导体器件。 该器件包括半导体衬底,场效应晶体管结构,其包括源区,第一体区,漏区,栅电极结构和栅极绝缘层。 栅极绝缘层设置在栅电极结构和体区之间。 栅极电极结构和漏极区域部分地形成电容器结构,其包括栅极 - 漏极电容,该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地 栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值,或者在给定的反向电压下包括平台状过程。

    SEMICONDUCTOR COMPONENT WITH TWO-STAGE BODY ZONE
    45.
    发明申请
    SEMICONDUCTOR COMPONENT WITH TWO-STAGE BODY ZONE 审中-公开
    具有两级机体区域的半导体组件

    公开(公告)号:US20090321818A1

    公开(公告)日:2009-12-31

    申请号:US12164611

    申请日:2008-06-30

    IPC分类号: H01L29/78 H01L21/336

    摘要: A semiconductor component with a two-stage body zone. One embodiment provides semiconductor component including a drift zone, and a compensation zone of a second conduction type. The compensation zone is arranged in the drift zone. A source zone and a body zone is provided. The body zone is arranged between the source zone and the drift zone. A gate electrode is arranged adjacent to the body zone. The body zone has a first body zone section and a second body zone section, which are adjacent to one another along the gate dielectric and of which the first body zone section is doped more highly than the second body zone section.

    摘要翻译: 具有两级体区的半导体元件。 一个实施例提供了包括漂移区和第二导电类型的补偿区的半导体元件。 补偿区设置在漂移区。 提供源区和体区。 身体区域布置在源区和漂移区之间。 栅电极邻近身体区域布置。 身体区域具有沿着栅极电介质彼此相邻的第一身体区段和第二身体区段部分,并且第一身体区域部分被掺杂得比第二身体区段更高。

    TRANSISTOR WITH CONTROLLABLE COMPENSATION REGIONS
    47.
    发明申请
    TRANSISTOR WITH CONTROLLABLE COMPENSATION REGIONS 有权
    具有可控制补偿区的晶体管

    公开(公告)号:US20120305993A1

    公开(公告)日:2012-12-06

    申请号:US13484490

    申请日:2012-05-31

    IPC分类号: H01L27/088

    摘要: A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.

    摘要翻译: 半导体器件包括栅极端子,至少一个控制端子以及第一和第二负载端子以及至少一个器件单元。 所述至少一个器件单元包括具有负载路径和控制端子的MOSFET器件,所述控制端子耦合到所述栅极端子以及具有负载路径和控制端子的JFET器件,所述负载路径与所述负载路径串联连接 的MOSFET器件在负载端子之间。 所述至少一个器件单元还包括具有负载路径和控制端子的第一耦合晶体管,所述负载路径耦合在所述JFET器件的控制端子与所述源极端子和所述栅极端子之一之间,并且所述控制端子耦合到 晶体管器件的至少一个控制端子。