公开(公告)号：US20080280416A1

公开(公告)日：2008-11-13

申请号：US12180827

申请日：2008-07-28

申请人： Stephen W. Bedell ,  Keith Edward Fogel ,  Bruce Kenneth Furman ,  Sampath Purushothaman ,  Devendra K. Sadana ,  Anna Wanda Topol

发明人： Stephen W. Bedell ,  Keith Edward Fogel ,  Bruce Kenneth Furman ,  Sampath Purushothaman ,  Devendra K. Sadana ,  Anna Wanda Topol

IPC分类号： H01L21/30 ,  H01L21/822

CPC分类号： H01L21/76259 ,  Y10T428/249961

摘要： Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein. In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a three dimensional integrated structure is provided.

摘要翻译： 提供了制造半导体器件的技术。 一方面，提供了层转移结构。 层转移结构包括具有调节孔隙度的多孔区域的载体衬底和在其中限定分离平面的注入物质的组合。 另一方面，提供了一种形成层转移结构的方法。 另一方面，提供一种形成三维一体化结构的方法。

公开(公告)号：US07397691B2

公开(公告)日：2008-07-08

申请号：US11409858

申请日：2006-04-24

申请人： Azeez Bhavnagarwala ,  Stephen V. Kosonocky ,  Sampath Purushothaman ,  Kenneth P. Rodbell

发明人： Azeez Bhavnagarwala ,  Stephen V. Kosonocky ,  Sampath Purushothaman ,  Kenneth P. Rodbell

IPC分类号： G11C11/00

CPC分类号： G11C11/4125 ,  Y10S257/903

摘要： A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.

摘要翻译： 存储单元包括字线，具有第一输入和第一输出的第一数字逆变器以及具有第二输入和第二输出的第二数字反相器。 此外，存储单元还包括将第一输出连接到第二输入的第一反馈连接和将第二输出连接到第一输入的第二反馈连接。 第一反馈连接包括第一电阻元件，第二反馈连接包括第二电阻元件。 更重要的是，每个数字逆变器都有相关的电容。 存储单元被配置为使得读取存储器单元包括将读取电压脉冲施加到字线。 此外，第一和第二电阻元件被配置为使得第一和第二反馈连接具有比施加的读取电压脉冲更长的电阻 - 电容感应延迟。

公开(公告)号：US20080122106A1

公开(公告)日：2008-05-29

申请号：US11518773

申请日：2006-09-11

申请人： Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Poncth

发明人： Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Matthew E. Colburn ,  Daniel C. Edelstein ,  Shom Poncth

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/7682

摘要： A structure and method to produce an airgap on a substrate having a dielectric layer with a pattern transferred onto the dielectric layer and a self aligned block out mask transferred on the dielectric layer around the pattern.

摘要翻译： 在具有转印到电介质层上的图案的电介质层和在图案周围的电介质层上转移的自对准阻挡掩模的衬底上产生气隙的结构和方法。

公开(公告)号：US20080042283A1

公开(公告)日：2008-02-21

申请号：US11857797

申请日：2007-09-19

申请人： Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Hosadurga Shobha ,  Terry Spooner

发明人： Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Hosadurga Shobha ,  Terry Spooner

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of fabricating the same in which the critical dimension of the conductive features are not altered by a plasma damaged layer are provided. In accordance with the present invention, a chemically etching dielectric material is subjected to a treatment step which modifies the density of the dielectric material such that the treated surfaces become denser than the bulk dielectric not subjected to the treatment. The treatment step is performed prior to deposition of the noble metal liner.

摘要翻译： 提供了一种互连结构及其制造方法，其中导电特征的临界尺寸不被等离子体损伤层改变。 根据本发明，对化学蚀刻介电材料进行处理步骤，该处理步骤改变介电材料的密度，使得处理的表面变得比不经受处理的体电介质更致密。 处理步骤在沉积贵金属衬垫之前进行。

公开(公告)号：US20060264036A1

公开(公告)日：2006-11-23

申请号：US11491816

申请日：2006-07-24

申请人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Matthew Colburn ,  Tomothy Dalton ,  Jeffrey Hedrick ,  Elbert Huang ,  Kaushik Kumar ,  Michael Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Robert Rosenberg ,  Christy Tyberg ,  Roy Yu

发明人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Matthew Colburn ,  Tomothy Dalton ,  Jeffrey Hedrick ,  Elbert Huang ,  Kaushik Kumar ,  Michael Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Robert Rosenberg ,  Christy Tyberg ,  Roy Yu

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

摘要翻译： 在多电平微电子集成电路中，空气包括永久线路电介质，超低K材料通过电介质。 在通过清洁热分解除去牺牲材料并通过IC结构中的孔隙率辅助副产物扩散后，将空气供应到线路电平。 任选地，空气也包括在通孔级电介质中的孔隙中。 通过将空气结合到本发明产生的程度，使层内和层间介电值最小化。

公开(公告)号：US20060103023A1

公开(公告)日：2006-05-18

申请号：US10988484

申请日：2004-11-12

申请人： Azeez Bhavnagarwala ,  Stephen Kosonocky ,  Satyanarayana Nitta ,  Sampath Purushothaman

发明人： Azeez Bhavnagarwala ,  Stephen Kosonocky ,  Satyanarayana Nitta ,  Sampath Purushothaman

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76801 ,  G11C11/412 ,  H01L23/53295 ,  H01L27/11 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip is described. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught.

摘要翻译： 描述了在一组区域中具有比在同一微电子芯片上的其它区域更高的互连电容的混合互连结构。 提供了几种制造这种结构的方法。 描述了这样的混合互连结构的电路实现，其能够增加静态噪声容限并且减少SRAM单元中的泄漏以及用于这种芯片中的SRAM和逻辑的公共电源电压。 还教导了能够将这些电路优点与更高的互连性能速度和优异的机械鲁棒性相结合的方法。

公开(公告)号：US20050272341A1

公开(公告)日：2005-12-08

申请号：US11150059

申请日：2005-06-10

申请人： Matthew Colburn ,  Satyanarayana Nitta ,  Sampath Purushothaman

发明人： Matthew Colburn ,  Satyanarayana Nitta ,  Sampath Purushothaman

IPC分类号： H01J9/14 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a low k, ultra-low k, and extreme-low k multilayer interconnect structure on a substrate in which the interconnect line features are separated laterally by a dielectric with vertically oriented nano-scale voids formed by perforating it using sub-optical lithography patterning and etching techniques and closing off the tops of the perforations by a dielectric deposition step. The lines are supported either by solid or patterned dielectric features underneath. The method avoids the issues associated with the formation of air gaps after the fabrication of conductor patterns and those associated with the integration of conventional low k, ultra-low k and extreme low k dielectrics which have porosity present before the formation of the interconnect patterns.

摘要翻译： 一种用于在衬底上制造低k，超低k和极低k多层互连结构的方法，其中互连线特征由具有垂直取向的纳米级空隙的电介质侧向分开， 光刻图案和蚀刻技术，并通过介电沉积步骤封闭穿孔的顶部。 线路由固体或图案化的电介质特征支撑。 该方法避免了在形成导体图案之后与形成气隙相关的问题，以及与形成互连图案之前具有孔隙率的常规低k，超低k和极低k电介质的集成相关联的问题。

公开(公告)号：US06930034B2

公开(公告)日：2005-08-16

申请号：US10331038

申请日：2002-12-27

申请人： Matthew E. Colburn ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Katherine L. Saenger

发明人： Matthew E. Colburn ,  Elbert E. Huang ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Katherine L. Saenger

IPC分类号： H01L23/12 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating low k and ultra-low k multilayer interconnect structures on a substrate includes: a set of interconnects separated laterally by air gaps; forming a support layer in the via level of a dual damascene structure that is only under the metal line; removing a sacrificial dielectric through a perforated bridge layer that connects the top surfaces of the interconnects laterally; performing multilevel extraction of a sacrificial layer; sealing the bridge in a controlled manner; and decreasing the effective dielectric constant of a membrane by perforating it using sub-optical lithography patterning techniques.

摘要翻译： 用于在衬底上制造低k和超低k多层互连结构的方法包括：一组通过气隙横向分离的互连; 在仅在金属线下面的双镶嵌结构的通孔层中形成支撑层; 通过横向连接互连的顶表面的穿孔桥接层去除牺牲电介质; 执行牺牲层的多级提取; 以受控的方式密封桥梁; 并通过使用亚光学光刻图案化技术对膜进行穿孔来降低膜的有效介电常数。

公开(公告)号：US20050079719A1

公开(公告)日：2005-04-14

申请号：US10683333

申请日：2003-10-10

申请人： Matthew Colburn ,  Satya Nitta ,  Sampath Purushothaman ,  Charles Black ,  Kathryn Guarini

发明人： Matthew Colburn ,  Satya Nitta ,  Sampath Purushothaman ,  Charles Black ,  Kathryn Guarini

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L23/52 ,  H05K3/10 ,  H05K3/46

CPC分类号： H01L21/31144 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.

摘要翻译： 描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧 具有盖电介质的孔阵列的顶部。 还描述了构建多层纳米柱状互连结构的方法和方法的变化。

公开(公告)号：US20050037604A1

公开(公告)日：2005-02-17

申请号：US10949837

申请日：2004-09-24

申请人： Katherina Babich ,  Roy Carruthers ,  Timothy Dalton ,  Alfred Grill ,  Jeffrey Hedrick ,  Christopher Jahnes ,  Ebony Mays ,  Laurent Perraud ,  Sampath Purushothaman ,  Katherine Saenger

发明人： Katherina Babich ,  Roy Carruthers ,  Timothy Dalton ,  Alfred Grill ,  Jeffrey Hedrick ,  Christopher Jahnes ,  Ebony Mays ,  Laurent Perraud ,  Sampath Purushothaman ,  Katherine Saenger

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/7681 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

摘要翻译： 描述了一种新颖的含气隙的互连布线结构，其在通孔级中结合有固体低k电介质，并且在布线层中结合了复合固体和气隙电介质。 还提供了形成这种互连结构的方法。 该方法很容易扩展到包含多个布线级别的互连结构，并且与双镶嵌后端（BEOL）处理兼容。